HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32380
Change subject: cpu/intel: Use system_reset() ......................................................................
cpu/intel: Use system_reset()
Use already defined system_reset() function.
Change-Id: I1f137611f46caddc5d4d356c73c4f335d030c1c8 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/fsp_model_406dx/bootblock.c M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/model_2065x/bootblock.c M src/cpu/intel/model_206ax/bootblock.c 4 files changed, 8 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/32380/1
diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index 14cfad9..009c09c 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -39,8 +39,7 @@ if ((inb(0xcf9) == 0x04) || (pci_io_read_config32(SOC_LPC_DEV, RCBA) & RCBA_ENABLE)) { - outb(0x00, 0xcf9); - outb(0x06, 0xcf9); + system_reset(); } }
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 722cc01..cdbd0ac 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -14,6 +14,7 @@ */
#include <stdint.h> +#include <cf9_reset.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -100,9 +101,7 @@ RCBA32_OR(SOFT_RESET_CTRL, 1);
/* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); + system_reset(); }
static void check_for_clean_reset(void) @@ -114,9 +113,7 @@ * Reset the system if any known bits are set in that MSR. That is * an indication of the CPU not being properly reset. */ if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) { - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); + system_reset(); } }
diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c index 19dbda8..693ae7a 100644 --- a/src/cpu/intel/model_2065x/bootblock.c +++ b/src/cpu/intel/model_2065x/bootblock.c @@ -15,6 +15,7 @@
#include <stdint.h> #include <arch/cpu.h> +#include <cf9_reset.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -104,9 +105,7 @@ RCBA32_OR(SOFT_RESET_CTRL, 1);
/* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); + system_reset(); }
static void bootblock_cpu_init(void) diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 9dcbe37..a7ba2030 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -15,6 +15,7 @@
#include <stdint.h> #include <arch/cpu.h> +#include <cf9_reset.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -106,9 +107,7 @@ RCBA32_OR(SOFT_RESET_CTRL, 1);
/* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); + system_reset(); }
static void bootblock_cpu_init(void)