Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39359 )
Change subject: soc/intel/tigerlake: Save DIMM info by available nodes ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39359/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39359/1//COMMIT_MSG@9 PS1, Line 9: TEST= make build image returns correct dimm info by mosys and dmidecode : with TGL-U and TGL-Y + MICA + LPDDR4
I think Nick mentioned that chromium coreboot boots up on volteer. Can you please check with him? […]
mosys now reports 8 devices @ x16 (instead of 4 devices):
localhost ~ #dmidecodemosys memory spd print geometryall 0 | LPDDR4 1 | LPDDR4 2 | LPDDR4 3 | LPDDR4 4 | LPDDR4 5 | LPDDR4 6 | LPDDR4 7 | LPDDR4 0 | 1-0 | 00000000 | None 1 | 1-0 | 00000000 | None 2 | 1-0 | 00000000 | None 3 | 1-0 | 00000000 | None 4 | 1-0 | 00000000 | None 5 | 1-0 | 00000000 | None 6 | 1-0 | 00000000 | None 7 | 1-0 | 00000000 | None 0 | 1024 | 1 | 16 1 | 1024 | 1 | 16 2 | 1024 | 1 | 16 3 | 1024 | 1 | 16 4 | 1024 | 1 | 16 5 | 1024 | 1 | 16 6 | 1024 | 1 | 16 7 | 1024 | 1 | 16 0 | LPDDR4-2133 1 | LPDDR4-2133 2 | LPDDR4-2133 3 | LPDDR4-2133 4 | LPDDR4-2133 5 | LPDDR4-2133 6 | LPDDR4-2133 7 | LPDDR4-2133 localhost~ #