[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training

[Subrata Banik (Code Review)]

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Vikrant L Jadeja.

Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email )

Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training
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Patch Set 15:

(1 comment)

File src/soc/intel/pantherlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/85454/comment/c9fb0def_8f1ea81d?usp... :
PS11, Line 375:
> This is not supported in the current design. I raised the point in December.

Please read my previous message as `CSE sync at ramstage` like what we did in MTL.
> I requested a mechanism for the bootloader (coreboot) to control VGA exit. Once available, I will push a new CL and update this function.

We should avoid tearing down the uGOP if CSE update is due. And CSE update can still show the VGA test msg. In case no CSE sync is pending, we can skip rendering CSE sync. due to CSE sync at pre-boot phase, we might not be able to check if CSE is booting from RO or RW (is_cse_boot_to_rw) as decision point to avoid tearing down of the uGOP eSOL like we did in MTL.