Andrey Petrov (andrey.petrov@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13640
-gerrit
commit 011af9086a77f7257d359b17cbedcec38109e010 Author: Andrey Petrov andrey.petrov@intel.com Date: Mon Feb 8 17:17:05 2016 -0800
arch/x86: Reserve space for stack in CAR layout
Some platforms may want to use C code in bootblock so they need writable memory and CAR can be used for it. This change reserves memory in CAR that can be used by bootblock and other CAR stages.
Change-Id: I8dec768cf8763dbe235f0ba1339079ebc49cbd9a Signed-off-by: Andrey Petrov andrey.petrov@intel.com --- src/arch/x86/car.ld | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 191dcaf..f29a465 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -23,6 +23,14 @@ #if IS_ENABLED(CONFIG_SEPARATE_VERSTAGE) VBOOT2_WORK(., 16K) #endif + /* Stack for CAR stages. Since it persists across all stages that + * use CAR it can be reused. The chipset/SoC is expected to provide + * the stack size. */ +#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) + _car_stack_start = .; + . += CONFIG_DCACHE_BSP_STACK_SIZE; + _car_stack_end = .; +#endif /* The pre-ram cbmem console as well as the timestamp region are fixed * in size. Therefore place them at the beginning .car.data section * so that multiple stages (romstage and verstage) have a consistent