[coreboot-gerrit] Change in coreboot[master]: nb/intel/haswell/memmap.c: Use ALIGN_DOWN(x, a)

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44924 )

Change subject: nb/intel/haswell/memmap.c: Use ALIGN_DOWN(x, a)
......................................................................

nb/intel/haswell/memmap.c: Use ALIGN_DOWN(x, a)

Also order and add missing includes.

Change-Id: I049441dd9074659effc1092dce08224974d60a2c
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/haswell/memmap.c
1 file changed, 4 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/44924/1

diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index a86efeb..2618754 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -4,11 +4,12 @@
 #define __SIMPLE_DEVICE__

#include <arch/romstage.h>
-#include <commonlib/helpers.h>
+#include <cbmem.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <device/pci_ops.h>
-#include <cbmem.h>
+#include <types.h>
+
 #include "haswell.h"

static uintptr_t smm_region_start(void)
@@ -18,7 +19,7 @@
     * 1 MiB alignment.
     */
    uintptr_t tom = pci_read_config32(HOST_BRIDGE, TSEG);
-	return tom & ~((1 << 20) - 1);
+	return ALIGN_DOWN(tom, 1 * MiB);
 }

void *cbmem_top_chipset(void)