Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42436 )
Change subject: mb/google/volteer: Override power limits with SKU-specific limits ......................................................................
mb/google/volteer: Override power limits with SKU-specific limits
Using guidance from Intel, a new set of power limits (PL1, PL2 & PL4) are available from. They are dependent upon the SKU of the CPU that the mainboard is running on. This is distinguished via System Agent PCI ID and the appropriate limits specified in devtree are overriden.
BUG=152639350 TEST=On a Volteer SKU4, verified the following console output: CPU TDP = 28 Watts CPU PL1 = 15 Watts CPU PL2 = 60 Watts CPU PL4 = 105 Watts
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0 --- M src/mainboard/google/volteer/mainboard.c 1 file changed, 41 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/42436/1
diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 1ede7f2..b24e97a 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -1,16 +1,16 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <console/console.h> #include <acpi/acpi.h> #include <baseboard/variants.h> #include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <ec/ec.h> #include <ec/google/chromeec/ec.h> #include <soc/gpio.h> +#include <soc/pci_devs.h> +#include <soc/soc_chip.h> #include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h>
@@ -25,6 +25,40 @@ dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; }
+static void override_power_limits(void) +{ + struct soc_intel_tigerlake_config *config; + struct device *sa; + uint16_t sa_pci_id; + + sa = pcidev_path_on_root(SA_DEVFN_ROOT); + sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF; + config = config_of_soc(); + + /* + * Reconfigure power limits depending on which processor SKU is on this particular + * mainboard. This is detected via System Agent PCI ID. + */ + switch (sa_pci_id) { + case PCI_DEVICE_ID_INTEL_TGL_ID_U: + case PCI_DEVICE_ID_INTEL_TGL_ID_U_1: + /* 4 cores, allow for higher power limits (in W) */ + config->power_limits_config.tdp_pl1_override = 15; + config->power_limits_config.tdp_pl2_override = 60; + config->power_limits_config.tdp_pl4 = 105; + break; + case PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2: + /* 2 cores, allow for lower power limits (in W) */ + config->power_limits_config.tdp_pl1_override = 15; + config->power_limits_config.tdp_pl2_override = 38; + config->power_limits_config.tdp_pl4 = 71; + break; + default: + printk(BIOS_ERR, "Volteer: unknown SA ID: 0x%4x", sa_pci_id); + break; + } +} + static void mainboard_chip_init(void *chip_info) { const struct pad_config *base_pads; @@ -36,6 +70,8 @@
gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); + + override_power_limits(); }
struct chip_operations mainboard_ops = {