Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10748
-gerrit
commit b5e02fd19ff71f9fd7c52904d549380507c943fa Author: Lee Leahy leroy.p.leahy@intel.com Date: Tue Jun 30 15:25:44 2015 -0700
Braswell: Add the GNVS pointer to the DSDT
Build the GNVS pointer and add it to the DSDT. With this patch, coreboot is able to boot ChromeOS without graphics.
BRANCH=none BUG=None TEST=Build and run on cyan
Change-Id: I8c7ae36b24da583928ad2532f611a855268b51f9 Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/soc/intel/braswell/southcluster.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 5a3ad9d..58237fa 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -21,10 +21,12 @@
#include <arch/io.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <bootstate.h> #include <cbmem.h> #include "chip.h" #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> @@ -34,6 +36,7 @@ #include <soc/iomap.h> #include <soc/irq.h> #include <soc/lpc.h> +#include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/ramstage.h> @@ -445,10 +448,35 @@ void southcluster_enable_dev(device_t dev) } }
+static void southcluster_inject_dsdt(device_t device) +{ + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + if (gnvs) + memset(gnvs, 0, sizeof(*gnvs)); + } + + if (gnvs) { + acpi_create_gnvs(gnvs); + acpi_save_gnvs((unsigned long)gnvs); + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + /* Add it to DSDT. */ + acpigen_write_scope("\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); + } +} + static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = NULL, + .acpi_inject_dsdt_generator = southcluster_inject_dsdt, .init = sc_init, .enable = southcluster_enable_dev, .scan_bus = scan_lpc_bus,