[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/ptl: Enable FSP debug log level control using CBFS

[Julius Werner (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik.

Julius Werner has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86002?usp=email )

Change subject: soc/intel/ptl: Enable FSP debug log level control using CBFS
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Patch Set 5:

(1 comment)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/86002/comment/9d3386f6_1aec67da?usp... :
PS5, Line 24: 	select HAVE_CBFS_FILE_OPTION_BACKEND if MAINBOARD_HAS_CHROMEOS
This really shouldn't be selected by an SoC Kconfig, it should either be enabled by CONFIG_CHROMEOS, or by our downstream ebuilds.