[coreboot-gerrit] Change in coreboot[master]: _WIP_ soc/amd/picasso: Begin programming UPD settings

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35275 )

Change subject: _WIP_ soc/amd/picasso: Begin programming UPD settings
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_WIP_ soc/amd/picasso: Begin programming UPD settings

Change-Id: I9c3f15c5de5ff38b532a9e803fdf18ba1bfc51c6
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/picasso/hybrid_romstage.c
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35275/1

diff --git a/src/soc/amd/picasso/hybrid_romstage.c b/src/soc/amd/picasso/hybrid_romstage.c
index d260513..fc79042 100644
--- a/src/soc/amd/picasso/hybrid_romstage.c
+++ b/src/soc/amd/picasso/hybrid_romstage.c
@@ -27,6 +27,7 @@
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/msr.h>
 #include <smp/node.h>
+#include <console/uart.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <commonlib/helpers.h>
@@ -134,7 +135,15 @@

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
+	FSP_M_CONFIG *mcfg = &mupd->FspmConfig;

+	mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
+
+	mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
+	mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
+	mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1;
+	mcfg->serial_port_baudrate = get_uart_baudrate();
+	mcfg->serial_port_refclk = uart_platform_refclk();
 }

asmlinkage void soc_hybrid_romstage_entry(uint32_t bist, uint64_t early_tsc)