Shelley Chen has uploaded a new change for review. ( https://review.coreboot.org/19554 )
Change subject: google/fizz: Configure SATAXPCIe GPIOs to use native function ......................................................................
google/fizz: Configure SATAXPCIe GPIOs to use native function
BUG=b:37486021, b:35775024 BRANCH=None TEST=reboot and ensure that device detects SSD
Change-Id: I4a85b9f3ba1d0a4c0a753420e166d3353417a1d1 Signed-off-by: Shelley Chen shchen@chromium.org --- M src/mainboard/google/fizz/gpio.h 1 file changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/19554/1
diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h index 1cd9d53..0950c76 100644 --- a/src/mainboard/google/fizz/gpio.h +++ b/src/mainboard/google/fizz/gpio.h @@ -143,9 +143,10 @@
/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */ -/* SATAXPCIE1 */ PAD_CFG_GPI(GPP_E1, NONE, DEEP), /* MB_PCIE_SATA#_DET */ -/* SATAXPCIE2 */ PAD_CFG_GPI(GPP_E2, 20K_PU, - DEEP), /* DB_PCIE_SATA#_DET */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, + NF1), /* MB_PCIE_SATA#_DET */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, + NF1), /* DB_PCIE_SATA#_DET */ /* CPU_GP0 */ PAD_CFG_NC(GPP_E3), /* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* DEVSLP0_MB */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_DB */