[coreboot-gerrit] Change in coreboot[master]: intel/broadwell: Use smm_subregion()

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34738 )

Change subject: intel/broadwell: Use smm_subregion()
......................................................................

intel/broadwell: Use smm_subregion()

Change-Id: I95f1685f9b74f68fd6cb681a614e52b8e0748216
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/include/soc/smm.h
M src/soc/intel/broadwell/memmap.c
M src/soc/intel/broadwell/smmrelocate.c
4 files changed, 57 insertions(+), 43 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/34738/1

diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 696cf98..5b29728 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -91,10 +91,6 @@
    hex
    default 0x800000

-config IED_REGION_SIZE
-	hex
-	default 0x400000
-
 config SMM_RESERVED_SIZE
    hex
    default 0x100000
diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h
index d3e1cdd..0c6f587 100644
--- a/src/soc/intel/broadwell/include/soc/smm.h
+++ b/src/soc/intel/broadwell/include/soc/smm.h
@@ -26,10 +26,10 @@
 } __packed;

struct smm_relocation_params {
-	u32 smram_base;
-	u32 smram_size;
-	u32 ied_base;
-	u32 ied_size;
+	uintptr_t smram_base;
+	size_t smram_size;
+	uintptr_t ied_base;
+	size_t ied_size;
    msr_t smrr_base;
    msr_t smrr_mask;
    msr_t emrr_base;
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index 7c53fa6..08d7b36 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -16,6 +16,7 @@
 #define __SIMPLE_DEVICE__

#include <cbmem.h>
+#include <cpu/x86/smm.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
@@ -46,14 +47,50 @@
    return (void *) dpr_region_start();
 }

-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	/* The ramstage cache lives in the TSEG region.
-	 * The top of RAM is defined to be the TSEG base address. */
-	u32 offset = smm_region_size();
-	offset -= CONFIG_IED_REGION_SIZE;
-	offset -= CONFIG_SMM_RESERVED_SIZE;
+	uintptr_t tseg = pci_read_config32(PCI_DEV(0, 0, 0), TSEG);
+	uintptr_t bgsm = pci_read_config32(PCI_DEV(0, 0, 0), BGSM);

-	*base = (void *)(cbmem_top() + offset);
-	*size = CONFIG_SMM_RESERVED_SIZE;
+	*start = tseg;
+	*size = bgsm - tseg;;
+}
+
+/* Intel Enhanced Debug region must be 4MB */
+#define FIXED_IED_REGION_SIZE	(4 << 20)
+
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
+{
+	uintptr_t sub_base;
+	size_t sub_size;
+	const size_t ied_size = FIXED_IED_REGION_SIZE;
+	const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
+
+	smm_region(&sub_base, &sub_size);
+
+	switch (sub) {
+	case SMM_SUBREGION_HANDLER:
+		/* Handler starts at the base of TSEG. */
+		sub_size -= ied_size;
+		sub_size -= cache_size;
+		break;
+	case SMM_SUBREGION_CACHE:
+		/* External cache is in the middle of TSEG. */
+		sub_base += sub_size - (ied_size + cache_size);
+		sub_size = cache_size;
+		break;
+	case SMM_SUBREGION_IED:
+		/* IED is at the top. */
+		sub_base += sub_size - ied_size;
+		sub_size = ied_size;
+		break;
+	default:
+		*start = 0;
+		*size = 0;
+		return -1;
+	}
+
+	*start = sub_base;
+	*size = sub_size;
+	return 0;
 }
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index 9ea73b2..7e893c1 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -179,22 +179,11 @@
    }
 }

-static u32 northbridge_get_base_reg(struct device *dev, int reg)
-{
-	u32 value;
-
-	value = pci_read_config32(dev, reg);
-	/* Base registers are at 1MiB granularity. */
-	value &= ~((1 << 20) - 1);
-	return value;
-}
-
 static void fill_in_relocation_params(struct device *dev,
    			      struct smm_relocation_params *params)
 {
-	u32 tseg_size;
-	u32 tsegmb;
-	u32 bgsm;
+	uintptr_t tseg_base;
+	size_t tseg_size;
    u32 emrr_base;
    u32 emrr_size;
    int phys_bits;
@@ -209,25 +198,17 @@
     * SMRAM range as well as the IED range. However, the SMRAM available
     * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB.
     */
-	tsegmb = northbridge_get_base_reg(dev, TSEG);
-	bgsm = northbridge_get_base_reg(dev, BGSM);
-	tseg_size = bgsm - tsegmb;
-
-	params->smram_base = tsegmb;
-	params->smram_size = 4 << 20;
-	params->ied_base = tsegmb + params->smram_size;
-	params->ied_size = tseg_size - params->smram_size;
-
-	/* Adjust available SMM handler memory size. */
-	params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
+	smm_region(&tseg_base, &tseg_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */
-	params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
+	params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
    params->smrr_base.hi = 0;
-	params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
-		| MTRR_PHYS_MASK_VALID;
+	params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
    params->smrr_mask.hi = 0;

+	smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
+	smm_subregion(SMM_SUBREGION_IED, &params->ied_base, &params->ied_size);
+
    /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
    emrr_base = (params->ied_base + (2 << 20)) & rmask;
    emrr_size = params->ied_size - (2 << 20);