Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55143 )
Change subject: soc/intel/alderlake: Set SaIpuEnable UPD from device state ......................................................................
soc/intel/alderlake: Set SaIpuEnable UPD from device state
The SaIpuEnable UPD is not currently being touched by coreboot; set it according to the enabled status of the corresponding devicetree node.
Change-Id: I53752f92c4b49093218cc34848727a72b63e84eb Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/55143/1
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index ba6e036..662db40 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -203,6 +203,10 @@ dev = pcidev_path_on_root(SA_DEVFN_TBT3); m_cfg->TcssItbtPcie3En = is_dev_enabled(dev);
+ /* IPU */ + dev = pcidev_path_on_root(SA_DEVFN_IPU); + m_cfg->SaIpuEnable = is_dev_enabled(dev); + /* VT-d config */ m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS; @@ -211,7 +215,8 @@ m_cfg->VtdDisable = 0; m_cfg->VtdIopEnable = !m_cfg->VtdDisable; m_cfg->VtdIgdEnable = m_cfg->InternalGfx; - m_cfg->VtdIpuEnable = m_cfg->SaIpuEnable; + dev = pcidev_path_on_root(SA_DEVFN_IPU); + m_cfg->VtdIpuEnable = is_dev_enabled(dev);
if (m_cfg->VtdIgdEnable && m_cfg->VtdBaseAddress[VTD_GFX] == 0) { m_cfg->VtdIgdEnable = 0;