[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Fix TSC frequency calculation

[Aaron Durbin (Code Review)]

Aaron Durbin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45055 )

Change subject: soc/amd/picasso: Fix TSC frequency calculation
......................................................................

soc/amd/picasso: Fix TSC frequency calculation

Fix TSC frequency calculation per Picasso PPR. This code was copied
from Stoney and was incorrect for Picasso.

BUG=b:163423984
TEST=verify Dalboz TSC to be 1GHz
BRANCH=zork

Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55
Signed-off-by: Nikolai Vyssotski 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45055
Tested-by: build bot (Jenkins) 
Reviewed-by: Marshall Dawson 
---
M src/soc/amd/picasso/tsc_freq.c
1 file changed, 17 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved

diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c
index a86080c..8a541fc 100644
--- a/src/soc/amd/picasso/tsc_freq.c
+++ b/src/soc/amd/picasso/tsc_freq.c
@@ -7,6 +7,10 @@

static unsigned long mhz;

+/* Use this default TSC frequency when it can not be correctly calculated.
+   Higher numbers are safer as it will result in longer delays using TSC */
+#define TSC_DEFAULT_FREQ_MHZ	4000
+
 unsigned long tsc_freq_mhz(void)
 {
    msr_t msr;
@@ -22,9 +26,19 @@
    if (!(msr.hi & 0x80000000))
    	die("Unknown error: cannot determine P-state 0\n");

-	cpufid = (msr.lo & 0x3f);
-	cpudid = (msr.lo & 0x1c0) >> 6;
+	cpufid = (msr.lo & 0xff);
+	cpudid = (msr.lo & 0x3f00) >> 8;

-	mhz = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
+	/* normally core frequency is calculated as (fid * 25) / (did / 8) */
+	if (!cpudid) {
+		mhz = TSC_DEFAULT_FREQ_MHZ;
+		printk(BIOS_ERR, "Invalid divisor, set TSC frequency to %ldMHz\n", mhz);
+	} else if ((cpudid >= 8) && (cpudid < 0x3c)) {
+		mhz = (200 * cpufid) / cpudid;
+	} else {
+		mhz = 25 * cpufid;
+		printk(BIOS_ERR, "Invalid frequency divisor 0x%x, assume 1\n", cpudid);
+	}
+
    return mhz;
 }