Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58541 )
Change subject: mainboard/starlabs: Add StarLite II, III & IV ......................................................................
mainboard/starlabs: Add StarLite II, III & IV
Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21
Everything works correctly.
https://starlabs.systems/pages/starlite-specification
Signed-off-by: Sean Rhodes sean@starlabs.systems Change-Id: I2d8adba834e5d42e3b8eae1dc38d925b0830c88d --- M Documentation/mainboard/index.md A Documentation/mainboard/starlabs/lite_apl.md A Documentation/mainboard/starlabs/lite_glk.md A Documentation/mainboard/starlabs/lite_glkr.md A src/mainboard/starlabs/lite/Kconfig A src/mainboard/starlabs/lite/Kconfig.name A src/mainboard/starlabs/lite/Makefile.inc A src/mainboard/starlabs/lite/acpi/mainboard.asl A src/mainboard/starlabs/lite/acpi/sleep.asl A src/mainboard/starlabs/lite/board.fmd A src/mainboard/starlabs/lite/board_info.txt A src/mainboard/starlabs/lite/bootblock.c A src/mainboard/starlabs/lite/cmos.default A src/mainboard/starlabs/lite/cmos.layout A src/mainboard/starlabs/lite/data.vbt A src/mainboard/starlabs/lite/devicetree.cb A src/mainboard/starlabs/lite/devtree.c A src/mainboard/starlabs/lite/dsdt.asl A src/mainboard/starlabs/lite/gma-mainboard.ads A src/mainboard/starlabs/lite/hda_verb.c A src/mainboard/starlabs/lite/mainboard.c A src/mainboard/starlabs/lite/ramstage.c A src/mainboard/starlabs/lite/variants/apl/Makefile.inc A src/mainboard/starlabs/lite/variants/apl/gpio.c A src/mainboard/starlabs/lite/variants/apl/romstage.c A src/mainboard/starlabs/lite/variants/baseboard/include/baseboard/variants.h A src/mainboard/starlabs/lite/variants/glk/Makefile.inc A src/mainboard/starlabs/lite/variants/glk/gpio.c A src/mainboard/starlabs/lite/variants/glk/romstage.c 29 files changed, 2,041 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/58541/1
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 7d701ee..b726c54 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -174,6 +174,9 @@
## Star Labs Systems
+- [StarLite Mk II](starlabs/lite_apl.md) +- [StarLite Mk III](starlabs/lite_glk.md) +- [StarLite Mk IV](starlabs/lite_glkr.md) - [LabTop Mk III](starlabs/labtop_kbl.md) - [LabTop Mk IV](starlabs/labtop_cml.md) - [StarBook Mk V](starlabs/starbook_tgl.md) diff --git a/Documentation/mainboard/starlabs/lite_apl.md b/Documentation/mainboard/starlabs/lite_apl.md new file mode 100644 index 0000000..c729dee --- /dev/null +++ b/Documentation/mainboard/starlabs/lite_apl.md @@ -0,0 +1,151 @@ +# Star Labs LabTop + +## Specs + +- CPU (full processor specs available at https://ark.intel.com) + - Intel N4200 (Apollo Lake) +- EC + - ITE IT8987E + - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - Charger, using AC adapter or USB-C PD + - Suspend / resume +- GPU + - Intel UHD Graphics 505 + - GOP driver is recommended, VBT is provided + - eDP 11.6-inch 1920x1080 LCD + - HDMI video + - USB-C DisplayPort video +- Memory + - 8GB on-board +- Networking + - 3165 CNVi WiFi / Bluetooth soldered to PCBA +- Sound + - Realtek ALC269 + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 SATA SSD + - RTS5129 MicroSD card reader +- USB + - 640x480 CCD camera + - USB 3.1 Gen 1 Type-C (left) + - USB 3.1 Gen 1 Type-A (left) + - USB 3.1 Gen 1 Type-A (right) + +## Building coreboot + +### Preliminaries + +Prior to building coreboot the following files are required: +* Intel Flash Descriptor file (descriptor.bin) + +All Star Labs platforms: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_apl +make +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | 25Q128JVSQ | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | no | ++---------------------+------------+ + +#### **Requirements:** + +* fwupd version 1.5.6 or later +* The battery must be charged to at least 30% +* The charger must be connected (either USB-C or DC Jack) +* BIOS Lock must be disabled +* Supported Linux distribution (Ubuntu 20.04 +, Linux Mint 20.1 + elementaryOS 6 +, Manjaro 21+) + +**fwupd 1.5.6 or later** +To check the version of **fwupd** you have installed, open a terminal window and enter the below command: + +``` +fwupdmgr --version +``` + +This will show the version number. **1.5.6** or greater will work. + +On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands: + +``` +sudo add-apt-repository ppa:starlabs/ppa +sudo apt update +sudo apt install fwupd +``` + +On Manjaro: + +``` +sudo pacman -Sy fwupd-git flashrom-starlabs +``` + +Instructions for other distributions will be added once fwupd 1.5.6 is available. If you are not using one of the distributions listed above, it is possible to install coreboot using a Live USB. + +**Disable BIOS Lock** +BIOS Lock must be disabled when switching from the standard AMI (American Megatrends Inc.) firmware to coreboot. To disable BIOS Lock: + +1. Start with your LabTop turned off. Turn it on whilst holding the **F2** key to access the BIOS settings. +2. When the BIOS settings load, use the arrow keys to navigate to the advanced tab. Here you will see BIOS Lock. +3. Press `Enter` to change this setting from **Enabled** to **Disabled** + + + +4. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm. + +#### **Switching Branch** + +Switching branch refers to changing from AMI firmware to coreboot, or vice versa. + +First, check for new firmware files with the below terminal command: + +``` +fwupdmgr refresh --force +``` + +Then, to change branch, enter the below terminal command: + +``` +fwupdmgr switch-branch +``` + +You can then select which branch you would like to use, by typing in the corresponding number: + +You will be prompted to confirm, press `y` to continue or `n` to cancel. + +Once the switch has been completed, you will be prompted to restart. + + +The next reboot can take up to **5 minutes,** do not interrupt this process or disconnect the charger. Once the reboot is complete, that's it - you'll continue to receive updates for whichever branch you are using. + +You can switch branch at any time. diff --git a/Documentation/mainboard/starlabs/lite_glk.md b/Documentation/mainboard/starlabs/lite_glk.md new file mode 100644 index 0000000..dac64d9 --- /dev/null +++ b/Documentation/mainboard/starlabs/lite_glk.md @@ -0,0 +1,151 @@ +# Star Labs LabTop + +## Specs + +- CPU (full processor specs available at https://ark.intel.com) + - Intel N5000 (Apollo Lake) +- EC + - ITE IT8987E + - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - Charger, using AC adapter or USB-C PD + - Suspend / resume +- GPU + - Intel UHD Graphics 605 + - GOP driver is recommended, VBT is provided + - eDP 11.6-inch 1920x1080 LCD + - HDMI video + - USB-C DisplayPort video +- Memory + - 8GB on-board +- Networking + - 9462 CNVi WiFi / Bluetooth soldered to PCBA +- Sound + - Realtek ALC269 + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 SATA SSD + - RTS5129 MicroSD card reader +- USB + - 640x480 CCD camera + - USB 3.1 Gen 1 Type-C (left) + - USB 3.1 Gen 1 Type-A (left) + - USB 3.1 Gen 1 Type-A (right) + +## Building coreboot + +### Preliminaries + +Prior to building coreboot the following files are required: +* Intel Flash Descriptor file (descriptor.bin) + +All Star Labs platforms: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glk +make +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | 25Q128JVSQ | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | no | ++---------------------+------------+ + +#### **Requirements:** + +* fwupd version 1.5.6 or later +* The battery must be charged to at least 30% +* The charger must be connected (either USB-C or DC Jack) +* BIOS Lock must be disabled +* Supported Linux distribution (Ubuntu 20.04 +, Linux Mint 20.1 + elementaryOS 6 +, Manjaro 21+) + +**fwupd 1.5.6 or later** +To check the version of **fwupd** you have installed, open a terminal window and enter the below command: + +``` +fwupdmgr --version +``` + +This will show the version number. **1.5.6** or greater will work. + +On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands: + +``` +sudo add-apt-repository ppa:starlabs/ppa +sudo apt update +sudo apt install fwupd +``` + +On Manjaro: + +``` +sudo pacman -Sy fwupd-git flashrom-starlabs +``` + +Instructions for other distributions will be added once fwupd 1.5.6 is available. If you are not using one of the distributions listed above, it is possible to install coreboot using a Live USB. + +**Disable BIOS Lock** +BIOS Lock must be disabled when switching from the standard AMI (American Megatrends Inc.) firmware to coreboot. To disable BIOS Lock: + +1. Start with your LabTop turned off. Turn it on whilst holding the **F2** key to access the BIOS settings. +2. When the BIOS settings load, use the arrow keys to navigate to the advanced tab. Here you will see BIOS Lock. +3. Press `Enter` to change this setting from **Enabled** to **Disabled** + + + +4. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm. + +#### **Switching Branch** + +Switching branch refers to changing from AMI firmware to coreboot, or vice versa. + +First, check for new firmware files with the below terminal command: + +``` +fwupdmgr refresh --force +``` + +Then, to change branch, enter the below terminal command: + +``` +fwupdmgr switch-branch +``` + +You can then select which branch you would like to use, by typing in the corresponding number: + +You will be prompted to confirm, press `y` to continue or `n` to cancel. + +Once the switch has been completed, you will be prompted to restart. + + +The next reboot can take up to **5 minutes,** do not interrupt this process or disconnect the charger. Once the reboot is complete, that's it - you'll continue to receive updates for whichever branch you are using. + +You can switch branch at any time. diff --git a/Documentation/mainboard/starlabs/lite_glkr.md b/Documentation/mainboard/starlabs/lite_glkr.md new file mode 100644 index 0000000..85f2a73 --- /dev/null +++ b/Documentation/mainboard/starlabs/lite_glkr.md @@ -0,0 +1,151 @@ +# Star Labs LabTop + +## Specs + +- CPU (full processor specs available at https://ark.intel.com) + - Intel N5030 (Apollo Lake) +- EC + - ITE IT8987E + - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - Charger, using AC adapter or USB-C PD + - Suspend / resume +- GPU + - Intel UHD Graphics 605 + - GOP driver is recommended, VBT is provided + - eDP 11.6-inch 1920x1080 LCD + - HDMI video + - USB-C DisplayPort video +- Memory + - 8GB on-board +- Networking + - 9461 CNVi WiFi / Bluetooth soldered to PCBA +- Sound + - Realtek ALC269 + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 SATA SSD + - RTS5129 MicroSD card reader +- USB + - 1600x1200 CCD camera + - USB 3.1 Gen 1 Type-C (left) + - USB 3.1 Gen 1 Type-A (left) + - USB 3.1 Gen 1 Type-A (right) + +## Building coreboot + +### Preliminaries + +Prior to building coreboot the following files are required: +* Intel Flash Descriptor file (descriptor.bin) + +All Star Labs platforms: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glkr +make +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | 25Q128JVSQ | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | no | ++---------------------+------------+ + +#### **Requirements:** + +* fwupd version 1.5.6 or later +* The battery must be charged to at least 30% +* The charger must be connected (either USB-C or DC Jack) +* BIOS Lock must be disabled +* Supported Linux distribution (Ubuntu 20.04 +, Linux Mint 20.1 + elementaryOS 6 +, Manjaro 21+) + +**fwupd 1.5.6 or later** +To check the version of **fwupd** you have installed, open a terminal window and enter the below command: + +``` +fwupdmgr --version +``` + +This will show the version number. **1.5.6** or greater will work. + +On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands: + +``` +sudo add-apt-repository ppa:starlabs/ppa +sudo apt update +sudo apt install fwupd +``` + +On Manjaro: + +``` +sudo pacman -Sy fwupd-git flashrom-starlabs +``` + +Instructions for other distributions will be added once fwupd 1.5.6 is available. If you are not using one of the distributions listed above, it is possible to install coreboot using a Live USB. + +**Disable BIOS Lock** +BIOS Lock must be disabled when switching from the standard AMI (American Megatrends Inc.) firmware to coreboot. To disable BIOS Lock: + +1. Start with your LabTop turned off. Turn it on whilst holding the **F2** key to access the BIOS settings. +2. When the BIOS settings load, use the arrow keys to navigate to the advanced tab. Here you will see BIOS Lock. +3. Press `Enter` to change this setting from **Enabled** to **Disabled** + + + +4. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm. + +#### **Switching Branch** + +Switching branch refers to changing from AMI firmware to coreboot, or vice versa. + +First, check for new firmware files with the below terminal command: + +``` +fwupdmgr refresh --force +``` + +Then, to change branch, enter the below terminal command: + +``` +fwupdmgr switch-branch +``` + +You can then select which branch you would like to use, by typing in the corresponding number: + +You will be prompted to confirm, press `y` to continue or `n` to cancel. + +Once the switch has been completed, you will be prompted to restart. + + +The next reboot can take up to **5 minutes,** do not interrupt this process or disconnect the charger. Once the reboot is complete, that's it - you'll continue to receive updates for whichever branch you are using. + +You can switch branch at any time. diff --git a/src/mainboard/starlabs/lite/Kconfig b/src/mainboard/starlabs/lite/Kconfig new file mode 100644 index 0000000..7050092 --- /dev/null +++ b/src/mainboard/starlabs/lite/Kconfig @@ -0,0 +1,80 @@ +config BOARD_STARLABS_LITE_SERIES + def_bool n + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_I2C_HID + select EC_STARLABS_ITE + select EC_STARLABS_KBL_LEVELS if BOARD_STARLABS_LITE_GLK + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select HAVE_INTEL_PTT + select HAVE_SMI_HANDLER + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select INTEL_LPSS_UART_FOR_CONSOLE + select NO_UART_ON_SUPERIO + select ONBOARD_VGA_IS_PRIMARY + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPI_FLASH_WINBOND + select SYSTEM_TYPE_LAPTOP + +config BOARD_STARLABS_LITE_APL + select BOARD_STARLABS_LITE_SERIES + select SOC_INTEL_APOLLOLAKE + +config BOARD_STARLABS_LITE_GLK + select BOARD_STARLABS_LITE_SERIES + select SOC_INTEL_GEMINILAKE + +config BOARD_STARLABS_LITE_GLKR + select BOARD_STARLABS_LITE_SERIES + select SOC_INTEL_GEMINILAKE + +if BOARD_STARLABS_LITE_SERIES + +config MAINBOARD_DIR + default "starlabs/lite" + +config VARIANT_DIR + default "apl" if BOARD_STARLABS_LITE_APL + default "glk" if BOARD_STARLABS_LITE_GLK || BOARD_STARLABS_LITE_GLKR + +config MAINBOARD_PART_NUMBER + default "Lite Mk II" if BOARD_STARLABS_LITE_APL + default "Lite Mk III" if BOARD_STARLABS_LITE_GLK + default "Lite Mk IV" if BOARD_STARLABS_LITE_GLKR + +config MAINBOARD_FAMILY + string + default "I2" if BOARD_STARLABS_LITE_APL + default "I3" if BOARD_STARLABS_LITE_GLK + default "I4" if BOARD_STARLABS_LITE_GLKR + +config MAINBOARD_SMBIOS_PRODUCT_NAME + string + default "Lite" + +config UART_FOR_CONSOLE + int + default 2 + +config FMDFILE + string + default "src/mainboard/starlabs/lite/board.fmd" + +config INTEL_GMA_VBT_FILE + string + default "src/mainboard/starlabs/lite/data.vbt" + +config IFD_BIN_PATH + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/$(CONFIG_VARIANT_DIR)/descriptor.bin" + +config TIANOCORE_BOOTSPLASH_FILE + string + depends on TIANOCORE_BOOTSPLASH_IMAGE + default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" + +endif diff --git a/src/mainboard/starlabs/lite/Kconfig.name b/src/mainboard/starlabs/lite/Kconfig.name new file mode 100644 index 0000000..41ea95c --- /dev/null +++ b/src/mainboard/starlabs/lite/Kconfig.name @@ -0,0 +1,11 @@ +comment "Star Labs Lite Series" + +config BOARD_STARLABS_LITE_APL + bool "Star Labs Lite Mk II (N4200)" + +config BOARD_STARLABS_LITE_GLK + bool "Star Labs Lite Mk III (N5000)" + +config BOARD_STARLABS_LITE_GLKR + bool "Star Labs Lite Mk IV (N5030)" + diff --git a/src/mainboard/starlabs/lite/Makefile.inc b/src/mainboard/starlabs/lite/Makefile.inc new file mode 100644 index 0000000..f21e7c0 --- /dev/null +++ b/src/mainboard/starlabs/lite/Makefile.inc @@ -0,0 +1,16 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +bootblock-y += bootblock.c + +ramstage-y += devtree.c +ramstage-y += hda_verb.c +ramstage-y += mainboard.c +ramstage-y += ramstage.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/starlabs/lite/acpi/mainboard.asl b/src/mainboard/starlabs/lite/acpi/mainboard.asl new file mode 100644 index 0000000..e65a6e5 --- /dev/null +++ b/src/mainboard/starlabs/lite/acpi/mainboard.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (_SB) { + #include "sleep.asl" +} + +/* + * The Intel Comet Lake platform doesn't support SoundWire but there + * is a kernel bug in some 5.10.x releases. + * + * Debian testing live CD (at 4th Feb 2021) uses 5.10.9-1. More + * details can be found at https://bit.ly/3ttdffG but it appears to + * be triggered by missing SoundWire ACPI entries. + * + * Add the minimal set to make it work again. + */ +Scope (_SB.PCI0.HDAS) +{ + Device (SNDW) + { + Name (_ADR, 0x40000000) + + Name (_CID, Package (0x02) + { + "PRP00001", + "PNP0A05" + }) + + Method (_STA, 0, NotSerialized) + { + Return (0x0B) + } + } +} diff --git a/src/mainboard/starlabs/lite/acpi/sleep.asl b/src/mainboard/starlabs/lite/acpi/sleep.asl new file mode 100644 index 0000000..85061fa --- /dev/null +++ b/src/mainboard/starlabs/lite/acpi/sleep.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (MPTS, 1, NotSerialized) // _PTS: Prepare To Sleep +{ + If (Arg0) + { + RPTS (Arg0) + } +} + +Method (MWAK, 1, NotSerialized) // _WAK: Wake +{ + RWAK (Arg0) + Return (0x00) +} diff --git a/src/mainboard/starlabs/lite/board.fmd b/src/mainboard/starlabs/lite/board.fmd new file mode 100644 index 0000000..837f0d6 --- /dev/null +++ b/src/mainboard/starlabs/lite/board.fmd @@ -0,0 +1,14 @@ +# +# Manually defined FMD in order to ensure that space is reserved for the EC +# at the top of the BIOS region. +# +FLASH 8M { + IFWI@0x0 + BIOS@0x200000 0x600000 { + RW_MRC_CACHE@0x0 0x10000 + SMMSTORE@0x10000 0x40000 + CONSOLE@0x50000 0x20000 + FMAP@0x70000 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/lite/board_info.txt b/src/mainboard/starlabs/lite/board_info.txt new file mode 100644 index 0000000..d4b4d4b --- /dev/null +++ b/src/mainboard/starlabs/lite/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Star Labs +Board name: Lite +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/starlabs/lite/bootblock.c b/src/mainboard/starlabs/lite/bootblock.c new file mode 100644 index 0000000..503fffd --- /dev/null +++ b/src/mainboard/starlabs/lite/bootblock.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <soc/gpio.h> + +#include "baseboard/variants.h" + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/starlabs/lite/cmos.default b/src/mainboard/starlabs/lite/cmos.default new file mode 100644 index 0000000..dc0451b --- /dev/null +++ b/src/mainboard/starlabs/lite/cmos.default @@ -0,0 +1,21 @@ +# hardcoded +boot_option=Fallback +# console +debug_level=Debug +# cpu +# hyper_threading=Enable +vtd=Enable +power_profile=Balanced +# me_state=Disable +# smi_handler=Enable +# Devices +wireless=Enable +webcam=Enable +microphone=Enable +legacy_8254_timer=Enable +usb_always_on=Disable +# EC +kbl_timeout=30 seconds +fn_ctrl_swap=Disable +# southbridge +power_on_after_fail=Disable diff --git a/src/mainboard/starlabs/lite/cmos.layout b/src/mainboard/starlabs/lite/cmos.layout new file mode 100644 index 0000000..c3b26a1 --- /dev/null +++ b/src/mainboard/starlabs/lite/cmos.layout @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# Bank: 1 +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level +# coreboot config options: cpu +#400 8 r 0 reserved for century byte +408 1 e 1 hyper_threading +416 1 e 1 vtd +424 2 e 7 power_profile +432 1 e 5 me_state +440 4 h 0 me_state_counter +448 1 e 1 smi_handler + +# coreboot config options: Devices +504 1 e 1 wireless +512 1 e 1 webcam +520 1 e 1 microphone +528 1 e 1 legacy_8254_timer +536 1 e 1 usb_always_on + +# coreboot config options: EC +600 3 e 4 kbl_timeout +608 1 e 1 fn_ctrl_swap +616 2 e 8 max_charge +624 2 e 9 fan_mode + +# coreboot config options: southbridge +800 2 e 6 power_on_after_fail + +# coreboot config options: check sums +984 16 h 0 check_sum + +# Bank: 2 +# embedded controller settings (outside the checksummed area) +1024 8 h 0 fn_lock_state +1032 8 h 0 trackpad_state +1040 8 h 0 kbl_brightness +1048 8 h 0 kbl_state + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Fallback +2 1 Normal + +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +4 0 30 seconds +4 1 1 minute +4 2 3 minutes +4 3 5 minutes +4 4 Never + +5 0 Enable +5 1 Disable + +6 0 Disable +6 1 Enable +6 2 Keep + +7 0 Power Saver +7 1 Balanced +7 2 Performance + +8 0 100% +8 1 80% +8 2 60% + +9 0 Normal +9 1 Aggressive +9 2 Quiet + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/starlabs/lite/data.vbt b/src/mainboard/starlabs/lite/data.vbt new file mode 100644 index 0000000..1f20023 --- /dev/null +++ b/src/mainboard/starlabs/lite/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/lite/devicetree.cb b/src/mainboard/starlabs/lite/devicetree.cb new file mode 100644 index 0000000..5ad1a98 --- /dev/null +++ b/src/mainboard/starlabs/lite/devicetree.cb @@ -0,0 +1,127 @@ +chip soc/intel/apollolake + +# CPU (soc/intel/apollolake/cpu.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 6, + }" + +# Graphics (soc/intel/apollolake/graphics.c) + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + # TODO: + # register "panel_cfg" = "{ + # .up_delay_ms = 0, // T3 + # .backlight_on_delay_ms = 0, // T7 + # .backlight_off_delay_ms = 0, // T9 + # .down_delay_ms = 0, // T10 + # .cycle_delay_ms = 500, // T12 + # .backlight_pwm_hz = 200, // PWM + # }" + +# PM Util (soc/intel/apollolake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + # + # Memory mapped at address 0x7f3a7eb8f000. + # Value at address 0xFE001920 (0x7f3a7eb8f920): 0xFFFFFFFF + # + register "gpe0_dw1" = "PMC_GPE_NW_63_32" + register "gpe0_dw2" = "PMC_GPE_NW_95_64" + register "gpe0_dw3" = "PMC_GPE_N_63_32" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + register "pnp_settings" = "PNP_PERF_POWER" + + register "pcie_rp_clkreq_pin[0]" = "2" # CNVi + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 00.1 on end # DPTF + device pci 00.2 off end # NPK + device pci 02.0 on end # Gen + device pci 03.0 off end # Iunit + device pci 0c.0 on end # CNVi + device pci 0d.0 off end # P2SB + device pci 0e.0 on # HDA + subsystemid 0x10ec 0x111e + end + device pci 0d.1 off end # PMC + device pci 0d.2 off end # SPI + device pci 0d.3 off end # Shared SRAM + device pci 0e.0 off end # Audio + device pci 0f.0 on end # Heci1 + device pci 0f.1 off end # Heci2 + device pci 0f.2 off end # Heci3 + device pci 11.0 off end # ISH + device pci 12.0 on end # SATA + device pci 13.0 off end # PCIe-A 0 Slot 1 + device pci 13.1 off end # PCIe-A 1 + device pci 13.2 off end # PCIe-A 2 Onboard Lan + device pci 13.3 off end # PCIe-A 3 + device pci 14.0 off end # PCIe-B 0 Slot2 + device pci 14.1 off end # PCIe-B 1 Onboard M2 Slot(Wifi/BT) + device pci 15.0 on end # XHCI + device pci 15.1 off end # XDCI + device pci 16.0 on # I2C 0 + chip drivers/i2c/hid + register "generic.hid" = ""STAR0001"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device pci 16.1 off end # I2C 1 + device pci 16.2 off end # I2C 2 + device pci 16.3 off end # I2C 3 + device pci 17.0 off end # I2C 4 + device pci 17.1 off end # I2C 5 + device pci 17.2 off end # I2C 6 + device pci 17.3 off end # I2C 7 + device pci 18.0 off end # UART 0 + device pci 18.1 off end # UART 1 + device pci 18.2 on end # UART 2 + device pci 18.3 off end # UART 3 + device pci 19.0 off end # SPI 0 + device pci 19.1 off end # SPI 1 + device pci 19.2 off end # SPI 2 + device pci 1a.0 off end # PWM + device pci 1b.0 off end # SDCARD + device pci 1c.0 off end # eMMC + device pci 1e.0 on end # SDIO + device pci 1f.0 on # LPC + # TODO: + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x680 - 0x68F + # register "gen1_dec" = "0x000c06a1" + # Address 0x88: Decode + # register "gen2_dec" = "0x000c0081" + + chip ec/starlabs/merlin + # Port 4Eh/4Fh + device pnp 4e.0 on + end + end + end + device pci 1f.1 on end # SMBUS + end +end diff --git a/src/mainboard/starlabs/lite/devtree.c b/src/mainboard/starlabs/lite/devtree.c new file mode 100644 index 0000000..74c1fe9 --- /dev/null +++ b/src/mainboard/starlabs/lite/devtree.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <chip.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <option.h> +#include <types.h> + +#include "baseboard/variants.h" + +struct device *variant_devtree_update(void) +{ + config_t *cfg = config_of_soc(); + struct soc_power_limits_config *soc_conf = &cfg->power_limits_config; + + /* Update PL2 based on CMOS settings */ + switch (get_uint_option("tdp", 0)) { + case 1: + soc_conf->tdp_pl1_override = 5; + soc_conf->tdp_pl2_override = 6; + break; + case 2: + soc_conf->tdp_pl1_override = 8; + soc_conf->tdp_pl2_override = 9; + break; + default: + soc_conf->tdp_pl1_override = 4; + soc_conf->tdp_pl2_override = 4; + break; + } + + /* Return the correct network device for this platform */ + return pcidev_on_root(0x0c, 0); +} diff --git a/src/mainboard/starlabs/lite/dsdt.asl b/src/mainboard/starlabs/lite/dsdt.asl new file mode 100644 index 0000000..8270788 --- /dev/null +++ b/src/mainboard/starlabs/lite/dsdt.asl @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x50 + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/apollolake/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) + { + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + /* Star Labs EC */ + #include <ec/starlabs/merlin/acpi/ec.asl> + + Scope (_SB) + { + /* HID Driver */ + #include <ec/starlabs/merlin/acpi/hid.asl> + + /* Suspend Methods */ + #include <ec/starlabs/merlin/acpi/suspend.asl> + } + + /* PS/2 Keyboard */ + Scope (_SB.PCI0) + { + // Add the entries for the PS/2 keyboard and mouse. + #include <drivers/pc80/pc/ps2_controller.asl> + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/starlabs/lite/gma-mainboard.ads b/src/mainboard/starlabs/lite/gma-mainboard.ads new file mode 100644 index 0000000..8402b39 --- /dev/null +++ b/src/mainboard/starlabs/lite/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- USB-C + HDMI1, -- USB-C + HDMI2, -- HDMI + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/starlabs/lite/hda_verb.c b/src/mainboard/starlabs/lite/hda_verb.c new file mode 100644 index 0000000..b8eb089 --- /dev/null +++ b/src/mainboard/starlabs/lite/hda_verb.c @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/azalia_device.h> + +#define AZALIA_CODEC_ALC269 0x10ec0269 + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269 + 0xffffffff, // Subsystem ID + 32, // Number of jacks (NID entries) + + /* Rest Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID Verb-table + HDA Codec Subsystem ID : 0x10EC111E */ + AZALIA_SUBVENDOR(0, 0x10EC111E), + + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x90171110), + AZALIA_PIN_CFG(0, 0x15, 0x042b1010), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x04ab1020), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x2e, 0x411111f0), + + /* RESET to D0 */ + 0x00170500, + 0x00170500, + 0x00170500, + 0x00170500, + + /* RESET Register */ + 0x0205001A, + 0x02048003, + 0x0205001A, + 0x0204C003, + + /* ALC256 default-1(Class D RESET) */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + + /* ALC256 default-2 */ + 0x02050040, + 0x02049800, + 0x02050034, + 0x0204023C, + + /* ALC256 Speaker output power - 4 ohm 2.2W (+12dB gain) + Combo Jack TRS setting */ + 0x02050038, + 0x02047901, + 0x02050045, + 0x02045089, + + /* H/W AGC setting-1 */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC2, + + /* H/W AGC setting-2 */ + 0x02050013, + 0x0204401D, + 0x02050016, + 0x02044E50, + + /* Zero data + EAPD to verb-control */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + + /* Zero data */ + 0x02050030, + 0x02048000, + 0x02050030, + 0x02048000, + + /* ALC256 default-3 */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + + /* ALC256 default-4 */ + 0x0205001B, + 0x02040A4B, + 0x02050008, + 0x02046A6C, + + /* JD1 */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + + /* Microphone + Array MIC security Disable +ADC clock Enable */ + 0x0205000D, + 0x0204A020, + 0x02050005, + 0x02040700, + + /* Speaker Enable */ + 0x0205000C, + 0x020401EF, + 0x0205000C, + 0x020401EF, + + /* EQ Bypass + EQ HPF cutoff 250Hz */ + 0x05350000, + 0x0534201A, + 0x0535001d, + 0x05340800, + + /* EQ-2 */ + 0x0535001e, + 0x05340800, + 0x05350003, + 0x05341EF8, + + /* EQ-3 */ + 0x05350004, + 0x05340000, + 0x05450000, + 0x05442000, + + /* EQ-4 */ + 0x0545001d, + 0x05440800, + 0x0545001e, + 0x05440800, + + /* EQ-5 */ + 0x05450003, + 0x05441EF8, + 0x05450004, + 0x05440000, + + /* EQ Update */ + 0x05350000, + 0x0534E01A, + 0x05350000, + 0x0534E01A, + + 0x8086280b, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 0x00000004, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/lite/mainboard.c b/src/mainboard/starlabs/lite/mainboard.c new file mode 100644 index 0000000..eede09d --- /dev/null +++ b/src/mainboard/starlabs/lite/mainboard.c @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <ec/starlabs/merlin/ec.h> +#include <limits.h> +#include <option.h> +#include <smbios.h> +#include <types.h> +#include <uuid.h> + +const char *smbios_mainboard_bios_version(void) +{ + return "8"; +} + +/* Get the Embedded Controller firmware version */ +void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) +{ + u16 ec_version = it_get_version(); + + *ec_major_revision = ec_version >> 8; + *ec_minor_revision = ec_version & 0xff; +} + +const char *smbios_system_manufacturer(void) +{ + return "Star Labs"; +} + +const char *smbios_system_sku(void) +{ + if (CONFIG(BOARD_STARLABS_LITE_GLK)) + return "I3"; + else if (CONFIG(BOARD_STARLABS_LITE_APL)) + return "I2"; + else + return "Unknown"; +} + +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} + +const char *smbios_mainboard_location_in_chassis(void) +{ + return "Default"; +} + +const char *smbios_mainboard_asset_tag(void) +{ + return "Default"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + +const char *smbios_chassis_version(void) +{ + return smbios_mainboard_version(); +} + +const char *smbios_chassis_serial_number(void) +{ + return smbios_mainboard_serial_number(); +} + +__weak struct device *variant_devtree_update(void) +{ + return NULL; +} + +/* Override dev tree settings based on CMOS settings */ +void devtree_update(void) +{ + struct device *nic_dev = NULL; + config_t *cfg = config_of_soc(); + + /* Perform any variant specific changes and return the nic_dev */ + nic_dev = variant_devtree_update(); + + if (nic_dev != NULL) { + if (get_uint_option("wireless", 1) == 0) + nic_dev->enabled = 0; + } + + if (get_uint_option("webcam", 1) == 0) + cfg->usb2_port[6].enable = 0; +} diff --git a/src/mainboard/starlabs/lite/ramstage.c b/src/mainboard/starlabs/lite/ramstage.c new file mode 100644 index 0000000..0437680 --- /dev/null +++ b/src/mainboard/starlabs/lite/ramstage.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <device/device.h> +#include <soc/ramstage.h> +#include <option.h> + +static void init_mainboard(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + + devtree_update(); +} + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/starlabs/lite/variants/apl/Makefile.inc b/src/mainboard/starlabs/lite/variants/apl/Makefile.inc new file mode 100644 index 0000000..7396e75 --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/apl/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +ramstage-y += gpio.c + +romstage-y += romstage.c + diff --git a/src/mainboard/starlabs/lite/variants/apl/gpio.c b/src/mainboard/starlabs/lite/variants/apl/gpio.c new file mode 100644 index 0000000..51187fe --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/apl/gpio.c @@ -0,0 +1,275 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "baseboard/variants.h" + +/* + * All definitions are taken from a comparison of the output of "inteltool -a" + * using the stock BIOS and with coreboot. + */ + +/* Early pad configuration in romstage.c */ +const struct pad_config early_gpio_table[] = { + _PAD_CFG_STRUCT(GPIO_64, 0x0006a0c5, 0x5f100002), + _PAD_CFG_STRUCT(GPIO_65, 0x0006a8c5, 0x5f100002), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage.c */ +const struct pad_config gpio_table[] = { + _PAD_CFG_STRUCT(GPIO_0, 0x000500c5, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_1, 0x000508c5, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_2, 0x000510c5, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_3, 0x000518c5, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_4, 0x000520c5, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_5, 0x000528c5, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_6, 0x000530c5, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_7, 0x000538c5, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_8, 0x000540c5, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_9, 0x000548c5, 0x01008008), + _PAD_CFG_STRUCT(GPIO_10, 0x000550c5, 0xa5001202), + _PAD_CFG_STRUCT(GPIO_11, 0x000558c5, 0x01008008), + _PAD_CFG_STRUCT(GPIO_12, 0x000560c5, 0x81008008), + _PAD_CFG_STRUCT(GPIO_13, 0x000568c5, 0x01008008), + _PAD_CFG_STRUCT(GPIO_14, 0x000570c5, 0x01008008), + _PAD_CFG_STRUCT(GPIO_15, 0x000578c5, 0x00008005), + _PAD_CFG_STRUCT(GPIO_16, 0x000580c5, 0x27009202), + _PAD_CFG_STRUCT(GPIO_17, 0x000588c5, 0x03008008), + _PAD_CFG_STRUCT(GPIO_18, 0x000590c5, 0x03008008), + _PAD_CFG_STRUCT(GPIO_19, 0x000598c5, 0x03008008), + _PAD_CFG_STRUCT(GPIO_20, 0x0005a0c5, 0x01008008), + _PAD_CFG_STRUCT(GPIO_21, 0x0005a8c5, 0x01008008), + _PAD_CFG_STRUCT(GPIO_22, 0x0005b0c5, 0x40008005), + _PAD_CFG_STRUCT(GPIO_23, 0x0005b8c5, 0x01008005), + _PAD_CFG_STRUCT(GPIO_24, 0x0005c0c5, 0x01008028), + _PAD_CFG_STRUCT(GPIO_25, 0x0005c8c5, 0x0100c102), + _PAD_CFG_STRUCT(GPIO_26, 0x0005d0c5, 0x01008028), + _PAD_CFG_STRUCT(GPIO_27, 0x0005d8c5, 0x1c108005), + _PAD_CFG_STRUCT(GPIO_28, 0x0005e0c5, 0x3d008010), + _PAD_CFG_STRUCT(GPIO_29, 0x0005e8c5, 0x3d008010), + _PAD_CFG_STRUCT(GPIO_30, 0x0005f0c5, 0x3d008008), + _PAD_CFG_STRUCT(GPIO_31, 0x0005f8c5, 0x3d008028), + _PAD_CFG_STRUCT(GPIO_32, 0x000600c5, 0x3d008028), + _PAD_CFG_STRUCT(GPIO_33, 0x000608c5, 0x3d008028), + _PAD_CFG_STRUCT(GPIO_34, 0x000610c5, 0x01008008), + _PAD_CFG_STRUCT(GPIO_35, 0x000618c5, 0x5d000002), + _PAD_CFG_STRUCT(GPIO_36, 0x000620c5, 0x01008008), + _PAD_CFG_STRUCT(GPIO_37, 0x000628c5, 0x00008008), + _PAD_CFG_STRUCT(GPIO_38, 0x000630c5, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_39, 0x000638c5, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_40, 0x000640c5, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_41, 0x000648c5, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_42, 0x000650c5, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_43, 0x000658c5, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_44, 0x000660c5, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_45, 0x000668c5, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_46, 0x000670c5, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_47, 0x000678c5, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_48, 0x000680c5, 0x5d000002), + _PAD_CFG_STRUCT(GPIO_49, 0x000688c5, 0x03008008), + _PAD_CFG_STRUCT(GPIO_62, 0x000690c5, 0x5f100002), + _PAD_CFG_STRUCT(GPIO_63, 0x000698c5, 0x5f100002), +// _PAD_CFG_STRUCT(GPIO_64, 0x0006a0c5, 0x5f100002), +// _PAD_CFG_STRUCT(GPIO_65, 0x0006a8c5, 0x5f100002), + _PAD_CFG_STRUCT(GPIO_66, 0x0006b0c5, 0x5f100002), + _PAD_CFG_STRUCT(GPIO_67, 0x0006b8c5, 0x5f000002), + _PAD_CFG_STRUCT(GPIO_68, 0x0006c0c5, 0x5f000002), + _PAD_CFG_STRUCT(GPIO_69, 0x0006c8c5, 0x5f000002), + _PAD_CFG_STRUCT(GPIO_70, 0x0006d0c5, 0x5f000002), + _PAD_CFG_STRUCT(GPIO_71, 0x0006d8c5, 0x5f000002), + _PAD_CFG_STRUCT(GPIO_72, 0x0006e0c5, 0x5f000002), + _PAD_CFG_STRUCT(GPIO_73, 0x0006e8c5, 0x5f000002), + _PAD_CFG_STRUCT(TCK, 0x0006f0c5, 0x3d008008), + _PAD_CFG_STRUCT(TRST_B, 0x0006f8c5, 0x3d008008), + _PAD_CFG_STRUCT(TMS, 0x000700c5, 0x3c108008), + _PAD_CFG_STRUCT(TDI, 0x000708c5, 0x3c108008), + _PAD_CFG_STRUCT(CX_PMODE, 0x000710c5, 0x3c008008), + _PAD_CFG_STRUCT(CX_PREQ_B, 0x000718c5, 0x3c108008), + _PAD_CFG_STRUCT(JTAGX, 0x000720c5, 0x3f008008), + _PAD_CFG_STRUCT(CX_PRDY_B, 0x000728c5, 0x3f008008), + _PAD_CFG_STRUCT(TDO, 0x000730c5, 0x3f008008), + _PAD_CFG_STRUCT(CNV_BRI_DT, 0x000738c5, 0x5d000002), + _PAD_CFG_STRUCT(CNV_BRI_RSP, 0x000740c5, 0x5d000002), + _PAD_CFG_STRUCT(CNV_RGI_DT, 0x000748c5, 0x5d000002), + _PAD_CFG_STRUCT(CNV_RGI_RSP, 0x000750c5, 0x5d000002), + _PAD_CFG_STRUCT(SVID0_ALERT_B, 0x000758c5, 0x1c108008), + _PAD_CFG_STRUCT(SVID0_DATA, 0x000760c5, 0x1c108008), + _PAD_CFG_STRUCT(SVID0_CLK, 0x000768c5, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_187, 0x000500c4, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_188, 0x000508c4, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_189, 0x000510c4, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_190, 0x000518c4, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_191, 0x000520c4, 0x01008008), + _PAD_CFG_STRUCT(GPIO_192, 0x000528c4, 0x01008008), + _PAD_CFG_STRUCT(GPIO_193, 0x000530c4, 0x05008008), + _PAD_CFG_STRUCT(GPIO_194, 0x000538c4, 0x05008008), + _PAD_CFG_STRUCT(GPIO_195, 0x000540c4, 0x05008008), + _PAD_CFG_STRUCT(GPIO_196, 0x000548c4, 0x41008005), + _PAD_CFG_STRUCT(GPIO_197, 0x000550c4, 0x41008005), + _PAD_CFG_STRUCT(GPIO_198, 0x000558c4, 0x41008005), + _PAD_CFG_STRUCT(GPIO_199, 0x000560c4, 0x1c108010), + _PAD_CFG_STRUCT(GPIO_200, 0x000568c4, 0x1c108010), + _PAD_CFG_STRUCT(GPIO_201, 0x000570c4, 0x05008008), + _PAD_CFG_STRUCT(GPIO_202, 0x000578c4, 0x05008008), + _PAD_CFG_STRUCT(GPIO_203, 0x000580c4, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_204, 0x000588c4, 0x1f108008), + _PAD_CFG_STRUCT(PMC_SPI_FS0, 0x000590c4, 0x03008008), + _PAD_CFG_STRUCT(PMC_SPI_FS1, 0x000598c4, 0x03008010), + _PAD_CFG_STRUCT(PMC_SPI_FS2, 0x0005a0c4, 0x03008008), + _PAD_CFG_STRUCT(PMC_SPI_RXD, 0x0005a8c4, 0x01008008), + _PAD_CFG_STRUCT(PMC_SPI_TXD, 0x0005b0c4, 0x01008008), + _PAD_CFG_STRUCT(PMC_SPI_CLK, 0x0005b8c4, 0x01008008), + _PAD_CFG_STRUCT(PMIC_PWRGOOD, 0x0005c0c4, 0x5c100002), + _PAD_CFG_STRUCT(PMIC_RESET_B, 0x0005c8c4, 0x5c100002), + _PAD_CFG_STRUCT(GPIO_213, 0x0005d0c4, 0x5c100002), + _PAD_CFG_STRUCT(GPIO_214, 0x0005d8c4, 0x5d000002), + _PAD_CFG_STRUCT(GPIO_215, 0x0005e0c4, 0x5d000002), + _PAD_CFG_STRUCT(PMIC_THERMTRIP_B, 0x0005e8c4, 0x3f008008), + _PAD_CFG_STRUCT(PMIC_STDBY, 0x0005f0c4, 0x5d000002), + _PAD_CFG_STRUCT(PROCHOT_B, 0x0005f8c4, 0x1f108008), + _PAD_CFG_STRUCT(PMIC_I2C_SCL, 0x000600c4, 0x3e408008), + _PAD_CFG_STRUCT(PMIC_I2C_SDA, 0x000608c4, 0x3e408008), + _PAD_CFG_STRUCT(GPIO_74, 0x000610c4, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_75, 0x000618c4, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_76, 0x000620c4, 0x41008005), + _PAD_CFG_STRUCT(GPIO_77, 0x000628c4, 0x01008002), + _PAD_CFG_STRUCT(GPIO_78, 0x000630c4, 0x01008002), + _PAD_CFG_STRUCT(GPIO_79, 0x000638c4, 0x3d008008), + _PAD_CFG_STRUCT(GPIO_80, 0x000640c4, 0x3d008008), + _PAD_CFG_STRUCT(GPIO_81, 0x000648c4, 0x25208008), + _PAD_CFG_STRUCT(GPIO_82, 0x000650c4, 0x3d008008), + _PAD_CFG_STRUCT(GPIO_83, 0x000658c4, 0x1d000008), + _PAD_CFG_STRUCT(GPIO_84, 0x000660c4, 0x01008010), + _PAD_CFG_STRUCT(GPIO_85, 0x000668c4, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_86, 0x000670c4, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_87, 0x000678c4, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_88, 0x000680c4, 0x1c100008), + _PAD_CFG_STRUCT(GPIO_89, 0x000688c4, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_90, 0x000690c4, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_91, 0x000698c4, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_92, 0x0006a0c4, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_97, 0x0006a8c4, 0x3fc08008), + _PAD_CFG_STRUCT(GPIO_98, 0x0006b0c4, 0x3fc08008), + _PAD_CFG_STRUCT(GPIO_99, 0x0006b8c4, 0x3fc08008), + _PAD_CFG_STRUCT(GPIO_100, 0x0006c0c4, 0x3fc08008), + _PAD_CFG_STRUCT(GPIO_101, 0x0006c8c4, 0x3fc08008), + _PAD_CFG_STRUCT(GPIO_102, 0x0006d0c4, 0x3fc08008), + _PAD_CFG_STRUCT(GPIO_103, 0x0006d8c4, 0x3fc08008), + _PAD_CFG_STRUCT(FST_SPI_CLK_FB, 0x0006e0c4, 0x3c008008), + _PAD_CFG_STRUCT(GPIO_104, 0x0006e8c4, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_105, 0x0006f0c4, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_106, 0x0006f8c4, 0x01008018), + _PAD_CFG_STRUCT(GPIO_109, 0x000700c4, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_110, 0x000708c4, 0x1d108008), + _PAD_CFG_STRUCT(GPIO_111, 0x000710c4, 0x41008002), + _PAD_CFG_STRUCT(GPIO_112, 0x000718c4, 0x01008010), + _PAD_CFG_STRUCT(GPIO_113, 0x000720c4, 0x41008002), + _PAD_CFG_STRUCT(GPIO_116, 0x000728c4, 0x01008010), + _PAD_CFG_STRUCT(GPIO_117, 0x000730c4, 0x01008010), + _PAD_CFG_STRUCT(GPIO_118, 0x000738c4, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_119, 0x000740c4, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_120, 0x000748c4, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_121, 0x000750c4, 0x01008008), + _PAD_CFG_STRUCT(GPIO_122, 0x000758c4, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_123, 0x000760c4, 0x1f008008), + _PAD_CFG_STRUCT(GPIO_124, 0x000500c7, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_125, 0x000508c7, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_126, 0x000510c7, 0x1ed08008), + _PAD_CFG_STRUCT(GPIO_127, 0x000518c7, 0x1ed08008), + _PAD_CFG_STRUCT(GPIO_128, 0x000520c7, 0x12708008), + _PAD_CFG_STRUCT(GPIO_129, 0x000528c7, 0x12708008), + _PAD_CFG_STRUCT(GPIO_130, 0x000530c7, 0x1ec08008), + _PAD_CFG_STRUCT(GPIO_131, 0x000538c7, 0x1ec08008), + _PAD_CFG_STRUCT(GPIO_132, 0x000540c7, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_133, 0x000548c7, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_134, 0x000550c7, 0x07308010), + _PAD_CFG_STRUCT(GPIO_135, 0x000558c7, 0x07308010), + _PAD_CFG_STRUCT(GPIO_136, 0x000560c7, 0x07308010), + _PAD_CFG_STRUCT(GPIO_137, 0x000568c7, 0x07308010), + _PAD_CFG_STRUCT(GPIO_138, 0x000570c7, 0x1ed08008), + _PAD_CFG_STRUCT(GPIO_139, 0x000578c7, 0x1ed08008), + _PAD_CFG_STRUCT(GPIO_146, 0x000580c7, 0x3d008018), + _PAD_CFG_STRUCT(GPIO_147, 0x000588c7, 0x3d008018), + _PAD_CFG_STRUCT(GPIO_148, 0x000590c7, 0x3d008018), + _PAD_CFG_STRUCT(GPIO_149, 0x000598c7, 0x3d008018), + _PAD_CFG_STRUCT(GPIO_150, 0x0005a0c7, 0x1d108010), + _PAD_CFG_STRUCT(GPIO_151, 0x0005a8c7, 0x41008004), + _PAD_CFG_STRUCT(GPIO_152, 0x0005b0c7, 0x01008010), + _PAD_CFG_STRUCT(GPIO_153, 0x0005b8c7, 0x3d008008), + _PAD_CFG_STRUCT(GPIO_155, 0x0005c8c7, 0x3d008010), + _PAD_CFG_STRUCT(GPIO_209, 0x0005d0c7, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_210, 0x0005d8c7, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_211, 0x0005e0c7, 0x1c108008), + _PAD_CFG_STRUCT(GPIO_212, 0x0005e8c7, 0x1c008008), + _PAD_CFG_STRUCT(OSC_CLK_OUT_0, 0x0005f0c7, 0x01008008), + _PAD_CFG_STRUCT(OSC_CLK_OUT_1, 0x0005f8c7, 0x01008008), + _PAD_CFG_STRUCT(OSC_CLK_OUT_2, 0x000600c7, 0x01008008), + _PAD_CFG_STRUCT(OSC_CLK_OUT_3, 0x000608c7, 0x01008008), + _PAD_CFG_STRUCT(OSC_CLK_OUT_4, 0x000610c7, 0x5d000002), + _PAD_CFG_STRUCT(PMU_AC_PRESENT, 0x000618c7, 0x3d008008), + _PAD_CFG_STRUCT(PMU_BATLOW_B, 0x000620c7, 0x3f008008), + _PAD_CFG_STRUCT(PMU_PLTRST_B, 0x000628c7, 0x3c108008), + _PAD_CFG_STRUCT(PMU_PWRBTN_B, 0x000630c7, 0x3f008008), + _PAD_CFG_STRUCT(PMU_RESETBUTTON_B, 0x000638c7, 0x3f008008), + _PAD_CFG_STRUCT(PMU_SLP_S0_B, 0x000640c7, 0x3c008008), + _PAD_CFG_STRUCT(PMU_SLP_S3_B, 0x000648c7, 0x3c008008), + _PAD_CFG_STRUCT(PMU_SLP_S4_B, 0x000650c7, 0x3c008008), + _PAD_CFG_STRUCT(PMU_SUSCLK, 0x000658c7, 0x1c108008), + _PAD_CFG_STRUCT(PMU_WAKE_B, 0x000660c7, 0x5d000002), + _PAD_CFG_STRUCT(SUS_STAT_B, 0x000668c7, 0x3c008008), + _PAD_CFG_STRUCT(SUSPWRDNACK, 0x000670c7, 0x3f008008), + _PAD_CFG_STRUCT(GPIO_205, 0x000500c0, 0x3f008008), + _PAD_CFG_STRUCT(GPIO_206, 0x000508c0, 0x3f008008), + _PAD_CFG_STRUCT(GPIO_207, 0x000510c0, 0x3f008008), + _PAD_CFG_STRUCT(GPIO_208, 0x000518c0, 0x3f008008), + _PAD_CFG_STRUCT(GPIO_154, 0x0005c0c7, 0x1c108005), + _PAD_CFG_STRUCT(GPIO_156, 0x000520c0, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_157, 0x000528c0, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_158, 0x000530c0, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_159, 0x000538c0, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_160, 0x000540c0, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_161, 0x000548c0, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_162, 0x000550c0, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_163, 0x000558c0, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_164, 0x000560c0, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_165, 0x000568c0, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_166, 0x000570c0, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_167, 0x000578c0, 0x1f008008), + _PAD_CFG_STRUCT(GPIO_168, 0x000580c0, 0x1f008008), + _PAD_CFG_STRUCT(GPIO_169, 0x000588c0, 0x1f008008), + _PAD_CFG_STRUCT(GPIO_170, 0x000590c0, 0x1f008008), + _PAD_CFG_STRUCT(GPIO_171, 0x000598c0, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_172, 0x0005a0c0, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_179, 0x0005a8c0, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_173, 0x0005b0c0, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_174, 0x0005b8c0, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_175, 0x0005c0c0, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_177, 0x0005d0c0, 0x64004002), + _PAD_CFG_STRUCT(GPIO_178, 0x0005d8c0, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_176, 0x0005c8c0, 0x1f108008), + _PAD_CFG_STRUCT(GPIO_186, 0x0005e0c0, 0x5c105004), + _PAD_CFG_STRUCT(GPIO_182, 0x0005e8c0, 0x1d008008), + _PAD_CFG_STRUCT(GPIO_183, 0x0005f0c0, 0x5c108005), + _PAD_CFG_STRUCT(SMB_ALERTB, 0x0005f8c0, 0x3f008008), + _PAD_CFG_STRUCT(SMB_CLK, 0x000600c0, 0x3f008008), + _PAD_CFG_STRUCT(SMB_DATA, 0x000608c0, 0x3f008008), + _PAD_CFG_STRUCT(LPC_ILB_SERIRQ, 0x000610c0, 0x3f008008), + _PAD_CFG_STRUCT(LPC_CLKOUT0, 0x000618c0, 0x1c108008), + _PAD_CFG_STRUCT(LPC_CLKOUT1, 0x000620c0, 0x3c008008), + _PAD_CFG_STRUCT(LPC_AD0, 0x000628c0, 0x1f108008), + _PAD_CFG_STRUCT(LPC_AD1, 0x000630c0, 0x1f108008), + _PAD_CFG_STRUCT(LPC_AD2, 0x000638c0, 0x1f108008), + _PAD_CFG_STRUCT(LPC_AD3, 0x000640c0, 0x1f108008), + _PAD_CFG_STRUCT(LPC_CLKRUNB, 0x000648c0, 0x1f008008), + _PAD_CFG_STRUCT(LPC_FRAMEB, 0x000650c0, 0x1f108008), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/lite/variants/apl/romstage.c b/src/mainboard/starlabs/lite/variants/apl/romstage.c new file mode 100644 index 0000000..c19bb44 --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/apl/romstage.c @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> +#include <soc/meminit.h> +#include <soc/romstage.h> +#include <string.h> + +static const uint8_t Ch0_Bit_swizzling[] = { + 0x11, 0x16, 0x13, 0x14, 0x15, 0x10, 0x12, 0x17, + 0x08, 0x0A, 0x0F, 0x0C, 0x09, 0x0D, 0x0B, 0x0E, + 0x01, 0x06, 0x07, 0x05, 0x00, 0x03, 0x02, 0x04, + 0x18, 0x1F, 0x19, 0x1D, 0x1E, 0x1B, 0x1A, 0x1C +}; +static const uint8_t Ch1_Bit_swizzling[] = { + 0x05, 0x06, 0x01, 0x00, 0x02, 0x04, 0x03, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0D, 0x0C, 0x0E, 0x0F, + 0x10, 0x14, 0x17, 0x12, 0x16, 0x13, 0x11, 0x15, + 0x1A, 0x18, 0x1F, 0x1B, 0x1C, 0x1D, 0x1E, 0x19 +}; +static const uint8_t Ch2_Bit_swizzling[] = { + 0x00, 0x0E, 0x0F, 0x09, 0x0A, 0x0B, 0x0C, 0x08, + 0x16, 0x15, 0x17, 0x11, 0x10, 0x14, 0x13, 0x12, + 0x02, 0x07, 0x05, 0x01, 0x06, 0x04, 0x00, 0x03, + 0x1F, 0x1A, 0x1B, 0x1D, 0x18, 0x19, 0x1C, 0x1E +}; +static const uint8_t Ch3_Bit_swizzling[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x06, 0x05, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x12, 0x11, 0x14, 0x16, 0x13, 0x15, 0x10, 0x17, + 0x18, 0x1A, 0x1D, 0x1C, 0x1B, 0x1F, 0x1E, 0x19 +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + memupd->FspmConfig.Package = 0x01, + memupd->FspmConfig.Profile = 0x05, + memupd->FspmConfig.MemoryDown = 0x01, + memupd->FspmConfig.DDR3LPageSize = 0x01, + memupd->FspmConfig.DDR3LASR = 0x00, + memupd->FspmConfig.ScramblerSupport = 0x01, + memupd->FspmConfig.ChannelHashMask = 0x00, + memupd->FspmConfig.SliceHashMask = 0x00, + memupd->FspmConfig.InterleavedMode = 0x00, + memupd->FspmConfig.ChannelsSlicesEnable = 0x00, + memupd->FspmConfig.MinRefRate2xEnable = 0x00, + memupd->FspmConfig.DualRankSupportEnable = 0x00, + memupd->FspmConfig.RmtMode = 0x00, + memupd->FspmConfig.MemorySizeLimit = 0x00, + memupd->FspmConfig.LowMemoryMaxValue = 0x00, + memupd->FspmConfig.DisableFastBoot = 0x00, + memupd->FspmConfig.HighMemoryMaxValue = 0x00, + memupd->FspmConfig.DIMM0SPDAddress = 0x00, + memupd->FspmConfig.DIMM1SPDAddress = 0x00, + + memupd->FspmConfig.Ch0_RankEnable = 0x03, + memupd->FspmConfig.Ch0_DeviceWidth = 0x02, + memupd->FspmConfig.Ch0_DramDensity = 0x02, + memupd->FspmConfig.Ch0_Option = 0x03, + memupd->FspmConfig.Ch0_OdtConfig = 0x00, + memupd->FspmConfig.Ch0_TristateClk1 = 0x00, + memupd->FspmConfig.Ch0_Mode2N = 0x00, + memupd->FspmConfig.Ch0_OdtLevels = 0x00, + + memupd->FspmConfig.Ch1_RankEnable = 0x03, + memupd->FspmConfig.Ch1_DeviceWidth = 0x02, + memupd->FspmConfig.Ch1_DramDensity = 0x02, + memupd->FspmConfig.Ch1_Option = 0x03, + memupd->FspmConfig.Ch1_OdtConfig = 0x00, + memupd->FspmConfig.Ch1_TristateClk1 = 0x00, + memupd->FspmConfig.Ch1_Mode2N = 0x00, + memupd->FspmConfig.Ch1_OdtLevels = 0x00, + + memupd->FspmConfig.Ch2_RankEnable = 0x03, + memupd->FspmConfig.Ch2_DeviceWidth = 0x02, + memupd->FspmConfig.Ch2_DramDensity = 0x02, + memupd->FspmConfig.Ch2_Option = 0x03, + memupd->FspmConfig.Ch2_OdtConfig = 0x00, + memupd->FspmConfig.Ch2_TristateClk1 = 0x00, + memupd->FspmConfig.Ch2_Mode2N = 0x00, + memupd->FspmConfig.Ch2_OdtLevels = 0x00, + + memupd->FspmConfig.Ch3_RankEnable = 0x03, + memupd->FspmConfig.Ch3_DeviceWidth = 0x02, + memupd->FspmConfig.Ch3_DramDensity = 0x02, + memupd->FspmConfig.Ch3_Option = 0x03, + memupd->FspmConfig.Ch3_OdtConfig = 0x00, + memupd->FspmConfig.Ch3_TristateClk1 = 0x00, + memupd->FspmConfig.Ch3_Mode2N = 0x00, + memupd->FspmConfig.Ch3_OdtLevels = 0x00, + + memupd->FspmConfig.RmtCheckRun = 0x00, + + memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, + sizeof(Ch0_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling, + sizeof(Ch1_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling, + sizeof(Ch2_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, + sizeof(Ch3_Bit_swizzling)); + + memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0; + memupd->FspmConfig.MsgLevelMask = 0x0; +} diff --git a/src/mainboard/starlabs/lite/variants/baseboard/include/baseboard/variants.h b/src/mainboard/starlabs/lite/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..c837d12 --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BASEBOARD_VARIANTS_H_ +#define _BASEBOARD_VARIANTS_H_ + +#include <soc/gpio.h> + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. + */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +void devtree_update(void); +struct device *variant_devtree_update(void); + +#endif /* _BASEBOARD_VARIANTS_H_ */ diff --git a/src/mainboard/starlabs/lite/variants/glk/Makefile.inc b/src/mainboard/starlabs/lite/variants/glk/Makefile.inc new file mode 100644 index 0000000..7396e75 --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/glk/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +ramstage-y += gpio.c + +romstage-y += romstage.c + diff --git a/src/mainboard/starlabs/lite/variants/glk/gpio.c b/src/mainboard/starlabs/lite/variants/glk/gpio.c new file mode 100644 index 0000000..3c9b7f6 --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/glk/gpio.c @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "baseboard/variants.h" + +/* + * All definitions are taken from a comparison of the output of "inteltool -a" + * using the stock BIOS and with coreboot. + */ + +/* Early pad configuration in romstage.c */ +const struct pad_config early_gpio_table[] = { + _PAD_CFG_STRUCT(GPIO_64, 0x0002336a, 0x44000402), + _PAD_CFG_STRUCT(GPIO_65, 0x0002336b, 0x44000400), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage.c */ +const struct pad_config gpio_table[] = { + _PAD_CFG_STRUCT(GPIO_0, 0x00c01000, 0x44000700), + _PAD_CFG_STRUCT(GPIO_1, 0x00c01000, 0x44000700), + _PAD_CFG_STRUCT(GPIO_2, 0x00c03000, 0x44000700), + _PAD_CFG_STRUCT(GPIO_3, 0x00c03000, 0x44000700), + _PAD_CFG_STRUCT(GPIO_4, 0x00c03000, 0x44000700), + _PAD_CFG_STRUCT(GPIO_5, 0x00c3c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_6, 0x00c3f300, 0x44000402), + _PAD_CFG_STRUCT(GPIO_7, 0x00c3f300, 0x44000402), + _PAD_CFG_STRUCT(GPIO_8, 0x0003c032, 0x04000300), + _PAD_CFG_STRUCT(GPIO_9, 0x0003c033, 0x04000300), + _PAD_CFG_STRUCT(GPIO_10, 0x0003c034, 0x04000300), + _PAD_CFG_STRUCT(GPIO_11, 0x0003c035, 0x04000300), + _PAD_CFG_STRUCT(GPIO_12, 0x0003c036, 0x04000300), + _PAD_CFG_STRUCT(GPIO_13, 0x0003c037, 0x44000300), + _PAD_CFG_STRUCT(GPIO_14, 0x00024038, 0x40800100), + _PAD_CFG_STRUCT(GPIO_15, 0x0003c039, 0x44000300), + _PAD_CFG_STRUCT(GPIO_16, 0x0003c03a, 0x44000300), + _PAD_CFG_STRUCT(GPIO_17, 0x0003c03b, 0x44000300), + _PAD_CFG_STRUCT(GPIO_18, 0x0003c03c, 0x44000300), + _PAD_CFG_STRUCT(GPIO_19, 0x0002733d, 0x42100102), + _PAD_CFG_STRUCT(GPIO_20, 0x0003c03e, 0x44000300), + _PAD_CFG_STRUCT(GPIO_21, 0x0000303f, 0x44000802), + _PAD_CFG_STRUCT(GPIO_22, 0x00027040, 0x44000800), + _PAD_CFG_STRUCT(GPIO_23, 0x00003041, 0x44000802), + _PAD_CFG_STRUCT(GPIO_24, 0x0003c042, 0x44000300), + _PAD_CFG_STRUCT(GPIO_25, 0x0003c043, 0x44000300), + _PAD_CFG_STRUCT(GPIO_26, 0x00024044, 0x40800102), + _PAD_CFG_STRUCT(GPIO_27, 0x00003045, 0x44000201), + _PAD_CFG_STRUCT(GPIO_28, 0x00003246, 0x44000201), + _PAD_CFG_STRUCT(GPIO_29, 0x00021147, 0x44000100), + _PAD_CFG_STRUCT(GPIO_30, 0x0003d048, 0x40900100), + _PAD_CFG_STRUCT(GPIO_31, 0x0003f049, 0x40900102), + _PAD_CFG_STRUCT(GPIO_32, 0x0003d24a, 0x44000100), + _PAD_CFG_STRUCT(GPIO_33, 0x0003f04b, 0x40900102), + _PAD_CFG_STRUCT(GPIO_34, 0x0003f34c, 0x44000201), + _PAD_CFG_STRUCT(GPIO_35, 0x0003d34d, 0x44000101), + _PAD_CFG_STRUCT(GPIO_36, 0x0003c34e, 0x44000300), + _PAD_CFG_STRUCT(GPIO_37, 0x0003c04f, 0x44000300), + _PAD_CFG_STRUCT(GPIO_38, 0x0003f350, 0x42880102), + _PAD_CFG_STRUCT(GPIO_39, 0x0003f351, 0x44000201), + _PAD_CFG_STRUCT(GPIO_40, 0x0003d352, 0x44000101), + _PAD_CFG_STRUCT(GPIO_41, 0x0003c053, 0x44000300), + _PAD_CFG_STRUCT(GPIO_42, 0x00001054, 0x44000700), + _PAD_CFG_STRUCT(GPIO_43, 0x00001055, 0x44000700), + _PAD_CFG_STRUCT(GPIO_44, 0x00003356, 0x44000402), + _PAD_CFG_STRUCT(GPIO_45, 0x00003357, 0x44000402), + _PAD_CFG_STRUCT(GPIO_46, 0x0003c058, 0x44000300), + _PAD_CFG_STRUCT(GPIO_47, 0x0003c059, 0x44000300), + _PAD_CFG_STRUCT(GPIO_48, 0x0003e75a, 0x44000402), + _PAD_CFG_STRUCT(GPIO_49, 0x0003e75b, 0x44000402), + _PAD_CFG_STRUCT(GPIO_50, 0x0002035c, 0x44000300), + _PAD_CFG_STRUCT(GPIO_51, 0x0002035d, 0x44000300), + _PAD_CFG_STRUCT(GPIO_52, 0x0003c05e, 0x44000300), + _PAD_CFG_STRUCT(GPIO_53, 0x0003c05f, 0x44000300), + _PAD_CFG_STRUCT(GPIO_54, 0x0003c060, 0x44000300), + _PAD_CFG_STRUCT(GPIO_55, 0x0003c061, 0x44000300), + _PAD_CFG_STRUCT(GPIO_56, 0x00022762, 0x44000402), + _PAD_CFG_STRUCT(GPIO_57, 0x00022763, 0x44000402), + _PAD_CFG_STRUCT(GPIO_58, 0x00022764, 0x44000402), + _PAD_CFG_STRUCT(GPIO_59, 0x00022765, 0x44000402), + _PAD_CFG_STRUCT(GPIO_60, 0x0003c066, 0x44000300), + _PAD_CFG_STRUCT(GPIO_61, 0x00003067, 0x44000300), + _PAD_CFG_STRUCT(GPIO_62, 0x0003c068, 0x44000300), + _PAD_CFG_STRUCT(GPIO_63, 0x0003c069, 0x44000300), +// _PAD_CFG_STRUCT(GPIO_64, 0x0002336a, 0x44000402), +// _PAD_CFG_STRUCT(GPIO_65, 0x0002336b, 0x44000400), + _PAD_CFG_STRUCT(GPIO_66, 0x0000336c, 0x44000201), + _PAD_CFG_STRUCT(GPIO_67, 0x0002036d, 0x44840102), + _PAD_CFG_STRUCT(GPIO_68, 0x0003c06e, 0x44000300), + _PAD_CFG_STRUCT(GPIO_69, 0x0003c06f, 0x44000300), + _PAD_CFG_STRUCT(GPIO_70, 0x0003c070, 0x44000300), + _PAD_CFG_STRUCT(GPIO_71, 0x0003c071, 0x44000300), + _PAD_CFG_STRUCT(GPIO_72, 0x0003c072, 0x44000300), + _PAD_CFG_STRUCT(GPIO_73, 0x0003c073, 0x44000300), + _PAD_CFG_STRUCT(GPIO_74, 0x0003f300, 0x44000400), + _PAD_CFG_STRUCT(GPIO_75, 0x00003000, 0x44000702), + _PAD_CFG_STRUCT(GPIO_211, 0xffffffff, 0xffffffff), + _PAD_CFG_STRUCT(GPIO_212, 0x0001d375, 0x44000102), + _PAD_CFG_STRUCT(GPIO_213, 0x0001d376, 0x44000102), + _PAD_CFG_STRUCT(GPIO_214, 0x0001d377, 0x44000102), + _PAD_CFG_STRUCT(GPIO_76, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_77, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_78, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_79, 0x0003d232, 0x44000400), + _PAD_CFG_STRUCT(GPIO_80, 0x0003d233, 0x44000400), + _PAD_CFG_STRUCT(GPIO_81, 0x0003d034, 0x44000c02), + _PAD_CFG_STRUCT(GPIO_82, 0x0003d235, 0x44000400), + _PAD_CFG_STRUCT(GPIO_83, 0x0003d236, 0x44000400), + _PAD_CFG_STRUCT(GPIO_84, 0x00001037, 0x44000100), + _PAD_CFG_STRUCT(GPIO_85, 0x00001038, 0x44000300), + _PAD_CFG_STRUCT(GPIO_86, 0x00001039, 0x44000300), + _PAD_CFG_STRUCT(GPIO_87, 0x0003c03a, 0x44000300), + _PAD_CFG_STRUCT(GPIO_88, 0x0003c03b, 0x44000300), + _PAD_CFG_STRUCT(GPIO_89, 0x0003c03c, 0x44000300), + _PAD_CFG_STRUCT(GPIO_90, 0x00003c3d, 0x44000502), + _PAD_CFG_STRUCT(GPIO_91, 0x0003c03e, 0x44000300), + _PAD_CFG_STRUCT(GPIO_92, 0x00003c3f, 0x44000500), + _PAD_CFG_STRUCT(GPIO_93, 0x00003c40, 0x44000502), + _PAD_CFG_STRUCT(GPIO_94, 0x00003c41, 0x44000502), + _PAD_CFG_STRUCT(GPIO_95, 0x00003c42, 0x44000502), + _PAD_CFG_STRUCT(GPIO_96, 0x00003c43, 0x44000500), + _PAD_CFG_STRUCT(GPIO_98, 0x00003c00, 0x44000500), + _PAD_CFG_STRUCT(GPIO_99, 0x00003200, 0x44000201), + _PAD_CFG_STRUCT(GPIO_100, 0x0003f300, 0x44000402), + _PAD_CFG_STRUCT(GPIO_101, 0x0003c000, 0x44000400), + _PAD_CFG_STRUCT(GPIO_102, 0x0003c000, 0x44000400), + _PAD_CFG_STRUCT(GPIO_103, 0x0003c000, 0x44000400), + _PAD_CFG_STRUCT(GPIO_104, 0x0003c000, 0x44000400), + _PAD_CFG_STRUCT(GPIO_105, 0x00003000, 0x44000700), + _PAD_CFG_STRUCT(GPIO_106, 0x00020344, 0x44000301), + _PAD_CFG_STRUCT(GPIO_107, 0x0003f300, 0x44000402), + _PAD_CFG_STRUCT(GPIO_108, 0x0003f300, 0x44000402), + _PAD_CFG_STRUCT(GPIO_109, 0x0003c000, 0x44000400), + _PAD_CFG_STRUCT(GPIO_110, 0x0003c000, 0x44000400), + _PAD_CFG_STRUCT(GPIO_111, 0x0003e745, 0x44000402), + _PAD_CFG_STRUCT(GPIO_112, 0x0003e746, 0x44000402), + _PAD_CFG_STRUCT(GPIO_113, 0x0003c047, 0x44000300), + _PAD_CFG_STRUCT(GPIO_114, 0x0003c048, 0x44000300), + _PAD_CFG_STRUCT(GPIO_115, 0x00022749, 0x44000402), + _PAD_CFG_STRUCT(GPIO_116, 0x0002274a, 0x44000402), + _PAD_CFG_STRUCT(GPIO_117, 0x0003f34b, 0x44000402), + _PAD_CFG_STRUCT(GPIO_118, 0x0003f34c, 0x44000402), + _PAD_CFG_STRUCT(GPIO_119, 0x0003f34d, 0x44000402), + _PAD_CFG_STRUCT(GPIO_120, 0x0003c04e, 0x44000300), + _PAD_CFG_STRUCT(GPIO_121, 0x0002334f, 0x44000402), + _PAD_CFG_STRUCT(GPIO_122, 0x00023350, 0x44000402), + _PAD_CFG_STRUCT(GPIO_123, 0x00023351, 0x44000402), + _PAD_CFG_STRUCT(GPIO_124, 0x00020352, 0x44000300), + _PAD_CFG_STRUCT(GPIO_125, 0x0001c353, 0x44000402), + _PAD_CFG_STRUCT(GPIO_126, 0x0001c354, 0x44000402), + _PAD_CFG_STRUCT(GPIO_127, 0x0003c055, 0x44000300), + _PAD_CFG_STRUCT(GPIO_128, 0x0003c056, 0x44000300), + _PAD_CFG_STRUCT(GPIO_129, 0x00005257, 0x44000400), + _PAD_CFG_STRUCT(GPIO_130, 0x00005258, 0x44000400), + _PAD_CFG_STRUCT(GPIO_131, 0x00005259, 0x44000400), + _PAD_CFG_STRUCT(GPIO_132, 0x0002735a, 0x44000402), + _PAD_CFG_STRUCT(GPIO_133, 0x0002735b, 0x44000402), + _PAD_CFG_STRUCT(GPIO_134, 0x0002435c, 0x44000400), + _PAD_CFG_STRUCT(GPIO_135, 0x0003f35d, 0x44000201), + _PAD_CFG_STRUCT(GPIO_136, 0x0000105e, 0x44000100), + _PAD_CFG_STRUCT(GPIO_137, 0x0003c05f, 0x44000300), + _PAD_CFG_STRUCT(GPIO_138, 0x0003c060, 0x44000300), + _PAD_CFG_STRUCT(GPIO_139, 0x00000061, 0x44000100), + _PAD_CFG_STRUCT(GPIO_140, 0x0003c062, 0x44000300), + _PAD_CFG_STRUCT(GPIO_141, 0x00003263, 0x44000201), + _PAD_CFG_STRUCT(GPIO_142, 0x00020364, 0x44000300), + _PAD_CFG_STRUCT(GPIO_143, 0x00023365, 0x44900102), + _PAD_CFG_STRUCT(GPIO_144, 0x00020066, 0x44900102), + _PAD_CFG_STRUCT(GPIO_145, 0x0003c067, 0x44000300), + _PAD_CFG_STRUCT(GPIO_146, 0x0003c068, 0x44000300), + _PAD_CFG_STRUCT(GPIO_147, 0x0003c069, 0x44000300), + _PAD_CFG_STRUCT(GPIO_148, 0x0000336a, 0x44000702), + _PAD_CFG_STRUCT(GPIO_149, 0x0002006b, 0x44000700), + _PAD_CFG_STRUCT(GPIO_150, 0x0002006c, 0x44000700), + _PAD_CFG_STRUCT(GPIO_151, 0x0002336d, 0x44000702), + _PAD_CFG_STRUCT(GPIO_152, 0x0002336e, 0x44000702), + _PAD_CFG_STRUCT(GPIO_153, 0x0002336f, 0x44000702), + _PAD_CFG_STRUCT(GPIO_154, 0x00023370, 0x44000702), + _PAD_CFG_STRUCT(GPIO_155, 0x00003071, 0x44000700), + _PAD_CFG_STRUCT(GPIO_156, 0x0003d200, 0x42000100), + _PAD_CFG_STRUCT(GPIO_157, 0x00003200, 0x44000201), + _PAD_CFG_STRUCT(GPIO_158, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_159, 0x00001000, 0x44000100), + _PAD_CFG_STRUCT(GPIO_160, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_161, 0x00001000, 0x44000100), + _PAD_CFG_STRUCT(GPIO_162, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_163, 0x0003f300, 0x44000201), + _PAD_CFG_STRUCT(GPIO_164, 0x00001000, 0x44000100), + _PAD_CFG_STRUCT(GPIO_165, 0x00003200, 0x44000201), + _PAD_CFG_STRUCT(GPIO_166, 0x00021200, 0x44000402), + _PAD_CFG_STRUCT(GPIO_167, 0x00021200, 0x44000400), + _PAD_CFG_STRUCT(GPIO_168, 0x00020000, 0x44000400), + _PAD_CFG_STRUCT(GPIO_169, 0x00021200, 0x44000400), + _PAD_CFG_STRUCT(GPIO_170, 0x00021200, 0x44000402), + _PAD_CFG_STRUCT(GPIO_171, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_172, 0x00001000, 0x44000100), + _PAD_CFG_STRUCT(GPIO_173, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_174, 0x00001300, 0x44000201), + _PAD_CFG_STRUCT(GPIO_175, 0x00001000, 0x44000100), + _PAD_CFG_STRUCT(GPIO_176, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_177, 0x0003c000, 0x40800102), + _PAD_CFG_STRUCT(GPIO_178, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_179, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_181, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_182, 0x00001200, 0x44000400), + _PAD_CFG_STRUCT(GPIO_183, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_184, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_185, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_186, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_187, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_188, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_210, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_189, 0x0001f200, 0x44000201), + _PAD_CFG_STRUCT(GPIO_190, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_191, 0x0003c000, 0x44000300), + _PAD_CFG_STRUCT(GPIO_192, 0x0003c000, 0x44000400), + _PAD_CFG_STRUCT(GPIO_193, 0x0003f300, 0x44000402), + _PAD_CFG_STRUCT(GPIO_194, 0x0003c000, 0x44000400), + _PAD_CFG_STRUCT(GPIO_195, 0x0003f300, 0x44000400), + _PAD_CFG_STRUCT(GPIO_196, 0x0003c000, 0x44000400), + _PAD_CFG_STRUCT(GPIO_198, 0x0003c000, 0x44000400), + _PAD_CFG_STRUCT(GPIO_200, 0x00001200, 0x44000b00), + _PAD_CFG_STRUCT(GPIO_201, 0x0001d200, 0x44000400), + _PAD_CFG_STRUCT(GPIO_202, 0x00001200, 0x44000500), + _PAD_CFG_STRUCT(GPIO_203, 0x00023300, 0x44000402), + _PAD_CFG_STRUCT(GPIO_204, 0x00023300, 0x44000402), + _PAD_CFG_STRUCT(GPIO_205, 0x00023300, 0x44000402), + _PAD_CFG_STRUCT(GPIO_206, 0x00023300, 0x44000402), + _PAD_CFG_STRUCT(GPIO_207, 0x00023300, 0x44000402), + _PAD_CFG_STRUCT(GPIO_208, 0x00023300, 0x44000402), + _PAD_CFG_STRUCT(GPIO_209, 0x00023300, 0x44000402), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/lite/variants/glk/romstage.c b/src/mainboard/starlabs/lite/variants/glk/romstage.c new file mode 100644 index 0000000..dd485e0 --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/glk/romstage.c @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> +#include <soc/meminit.h> +#include <soc/romstage.h> +#include <string.h> + +static const uint8_t Ch0_Bit_swizzling[] = { + 0x0F, 0x0B, 0x0D, 0X0E, 0x09, 0x0C, 0x0A, 0x08, + 0x06, 0x04, 0x05, 0x07, 0x03, 0x02, 0x01, 0x00, + 0x1E, 0x19, 0x18, 0x1C, 0x1D, 0x1B, 0x1F, 0x1A, + 0x14, 0x15, 0x17, 0x10, 0x16, 0x12, 0x11, 0x13 +}; +static const uint8_t Ch1_Bit_swizzling[] = { + 0x03, 0x05, 0x06, 0x07, 0x01, 0x04, 0x02, 0x00, + 0x0C, 0x0D, 0X0E, 0x0B, 0x0A, 0x08, 0x09, 0X0F, + 0x10, 0x16, 0x15, 0x13, 0x14, 0x17, 0x12, 0x11, + 0x1F, 0x1E, 0x1B, 0x19, 0x18, 0x1D, 0x1C, 0x1A +}; +static const uint8_t Ch2_Bit_swizzling[] = { + 0x08, 0X0D, 0x0B, 0x0E, 0x09, 0X0F, 0x0C, 0X0A, + 0x04, 0x00, 0x02, 0x06, 0x05, 0x07, 0x03, 0x01, + 0x1B, 0x1C, 0x15, 0x1D, 0x1A, 0x18, 0x19, 0x1E, + 0x17, 0x12, 0x15, 0x16, 0x13, 0x10, 0x14, 0x11 +}; +static const uint8_t Ch3_Bit_swizzling[] = { + 0x03, 0x07, 0x06, 0x05, 0x01, 0x04, 0x02, 0x00, + 0x0C, 0x0F, 0x0D, 0X0E, 0X0A, 0x08, 0x09, 0x0B, + 0x10, 0x11, 0x12, 0x13, 0x16, 0x14, 0x17, 0x15, + 0x1C, 0x1E, 0x1D, 0x19, 0x1F, 0x18, 0x18, 0x1A +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + memupd->FspmConfig.Package = 0x01, + memupd->FspmConfig.Profile = 0x0B, + memupd->FspmConfig.MemoryDown = 0x01, + memupd->FspmConfig.DDR3LPageSize = 0x00, + memupd->FspmConfig.DDR3LASR = 0x00, + memupd->FspmConfig.ScramblerSupport = 0x01, + memupd->FspmConfig.ChannelHashMask = 0x36, + memupd->FspmConfig.SliceHashMask = 0x09, + memupd->FspmConfig.InterleavedMode = 0x02, + memupd->FspmConfig.ChannelsSlicesEnable = 0x00, + memupd->FspmConfig.MinRefRate2xEnable = 0x00, + memupd->FspmConfig.DualRankSupportEnable = 0x01, + memupd->FspmConfig.RmtMode = 0x00, + memupd->FspmConfig.MemorySizeLimit = 0x00, + memupd->FspmConfig.LowMemoryMaxValue = 0x00, + memupd->FspmConfig.DisableFastBoot = 0x00, + memupd->FspmConfig.HighMemoryMaxValue = 0x00, + memupd->FspmConfig.DIMM0SPDAddress = 0x00, + memupd->FspmConfig.DIMM1SPDAddress = 0x00, + + memupd->FspmConfig.Ch0_RankEnable = 0x03, + memupd->FspmConfig.Ch0_DeviceWidth = 0x01, + memupd->FspmConfig.Ch0_DramDensity = 0x02, + memupd->FspmConfig.Ch0_Option = 0x03, + memupd->FspmConfig.Ch0_OdtConfig = 0x02, + memupd->FspmConfig.Ch0_TristateClk1 = 0x00, + memupd->FspmConfig.Ch0_Mode2N = 0x00, + memupd->FspmConfig.Ch0_OdtLevels = 0x00, + + memupd->FspmConfig.Ch1_RankEnable = 0x03, + memupd->FspmConfig.Ch1_DeviceWidth = 0x01, + memupd->FspmConfig.Ch1_DramDensity = 0x02, + memupd->FspmConfig.Ch1_Option = 0x03, + memupd->FspmConfig.Ch1_OdtConfig = 0x02, + memupd->FspmConfig.Ch1_TristateClk1 = 0x00, + memupd->FspmConfig.Ch1_Mode2N = 0x00, + memupd->FspmConfig.Ch1_OdtLevels = 0x00, + + memupd->FspmConfig.Ch2_RankEnable = 0x03, + memupd->FspmConfig.Ch2_DeviceWidth = 0x01, + memupd->FspmConfig.Ch2_DramDensity = 0x02, + memupd->FspmConfig.Ch2_Option = 0x03, + memupd->FspmConfig.Ch2_OdtConfig = 0x02, + memupd->FspmConfig.Ch2_TristateClk1 = 0x00, + memupd->FspmConfig.Ch2_Mode2N = 0x00, + memupd->FspmConfig.Ch2_OdtLevels = 0x00, + + memupd->FspmConfig.Ch3_RankEnable = 0x03, + memupd->FspmConfig.Ch3_DeviceWidth = 0x01, + memupd->FspmConfig.Ch3_DramDensity = 0x02, + memupd->FspmConfig.Ch3_Option = 0x03, + memupd->FspmConfig.Ch3_OdtConfig = 0x02, + memupd->FspmConfig.Ch3_TristateClk1 = 0x00, + memupd->FspmConfig.Ch3_Mode2N = 0x00, + memupd->FspmConfig.Ch3_OdtLevels = 0x00, + + memupd->FspmConfig.RmtCheckRun = 0x00, + + memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, + sizeof(Ch0_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling, + sizeof(Ch1_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling, + sizeof(Ch2_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, + sizeof(Ch3_Bit_swizzling)); + + memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0; + memupd->FspmConfig.MsgLevelMask = 0x0; +}