Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64855 )
Change subject: soc/intel/cmn/cse: Implement heci_init() to initialize HECI devices ......................................................................
soc/intel/cmn/cse: Implement heci_init() to initialize HECI devices
This patch implements heci_init() API that perform initialization of all HECI devices as per MAX_HECI_DEVICES config.
BUG=none TEST=TBD
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: Ia25e18a20cc749fc7eee39b0b591d41540fc14c9 --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 42 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/64855/1
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index e01b1cf..5da3a6f 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -23,6 +23,8 @@ #include <timer.h> #include <types.h>
+#define HECI_BASE_SIZE (4 * KiB) + #define MAX_HECI_MESSAGE_RETRY_COUNT 5
/* Wait up to 15 sec for HECI to get ready */ @@ -84,6 +86,24 @@ return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; }
+static void heci_assign_resource(pci_devfn_t dev, uintptr_t tempbar) +{ + u16 pcireg; + + /* Assign Resources */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config16(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config16(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for HECI device */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); + + /* Enable Bus Master and MMIO Space */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); +} + /* * Initialize the CSE device with provided temporary BAR. If BAR is 0 use a * default. This is intended for pre-mem usage only where BARs haven't been @@ -93,8 +113,6 @@ { pci_devfn_t dev = PCH_DEV_CSE;
- u16 pcireg; - /* Check if device enabled */ if (!is_cse_enabled()) return; @@ -107,18 +125,8 @@ if (!tempbar) tempbar = HECI1_BASE_ADDRESS;
- /* Assign Resources to HECI1 */ - /* Clear BIT 1-2 of Command Register */ - pcireg = pci_read_config16(dev, PCI_COMMAND); - pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config16(dev, PCI_COMMAND, pcireg); - - /* Program Temporary BAR for HECI1 */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); - pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); - - /* Enable Bus Master and MMIO Space */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + /* Assign HECI resource and enable the resource */ + heci_assign_resource(dev, tempbar);
/* Trigger HECI Reset and make Host ready for communication with CSE */ heci_reset(); @@ -1020,6 +1028,23 @@ } }
+/* Initialize the HECI devices. */ +void heci_init(void) +{ + uintptr_t tempbar = HECI1_BASE_ADDRESS; + + for (int i = 0; i < CONFIG_MAX_HECI_DEVICES; i++) { + pci_devfn_t dev = PCI_DEVFN(PCH_DEV_SLOT_CSE, i); + if (!is_cse_devfn_visible(dev)) + continue; + + tempbar += (i * HECI_BASE_SIZE); + heci_assign_resource(dev, tempbar); + + ensure_cse_active(dev); + } +} + void cse_control_global_reset_lock(void) { /* diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 28bc250..322e9f3 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -333,6 +333,9 @@ */ void cse_init(uintptr_t bar);
+/* Initialize the HECI devices. */ +void heci_init(void); + /* * Send message from BIOS_HOST_ADDR to cse_addr. * Sends snd_msg of size snd_sz, and reads message into buffer pointed by