Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/systemagent.asl:
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 185: #if !CONFIG(TPM_CR50)
basically this reservation is true for all TPM device using TIS interface using SOC bus like LPC, SP […]
This is the confusing part: While TIS assumes that a SPI TPM has memory-mapped registers, nothing for coreboot's SPI_TPM or I2C_TPM looks like that would be the case. I guess one would have to attach a TPM to the "Fast SPI" interface of an Intel SoC to get memory-mapping, but that's not supported by SPI_TPM, it seems.
Also, CR50 implies SPI_TPM || I2C_TPM.
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 190: 0x00005000) All the #if aside, where is it written that the PCH doesn't decode this range when there is no (compatible) TPM attached?