[coreboot-gerrit] Change in ...coreboot[master]: mb/ocp/wedge100s: Fix devicetree

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31228 )

Change subject: mb/ocp/wedge100s: Fix devicetree
......................................................................

mb/ocp/wedge100s: Fix devicetree

Match devicetree what's present and in use.

Tested on wedge100s:
All PCI devices show up.

Change-Id: I669d059da1876ed669793db8c7eb1b96b481cb4c
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/31228
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
Reviewed-by: Paul Menzel 
Reviewed-by: Felix Held 
Reviewed-by: Angel Pons 
---
M src/mainboard/ocp/wedge100s/devicetree.cb
1 file changed, 24 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Felix Held: Looks good to me, approved
  Arthur Heymans: Looks good to me, but someone else must approve
  Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/ocp/wedge100s/devicetree.cb b/src/mainboard/ocp/wedge100s/devicetree.cb
index bbea89e..48410ba 100644
--- a/src/mainboard/ocp/wedge100s/devicetree.cb
+++ b/src/mainboard/ocp/wedge100s/devicetree.cb
@@ -4,10 +4,26 @@
    end
    device domain 0 on
    	device pci 00.0 on end # SoC router
-		device pci 14.0 on end # xHCI Controller
-		device pci 19.0 on end # Gigabit LAN Controller
-		device pci 1d.0 on end # EHCI Controller
-		device pci 1f.0 on
+		device pci 01.0 on # PCIe x1
+			# Intel i210t
+		end
+		device pci 02.0 on # PCIe x1
+			# QuickData Technology
+		end
+		device pci 02.2 on # PCIe x1
+			# Intel X552 10 GbE SFP+
+		end
+		device pci 03.0 on end # PEG 16x
+		device pci 05.0 on end # Vtd
+		device pci 05.1 on end # IIO Hotplug
+		device pci 05.2 on end # IIO
+		device pci 05.4 on end # PIC
+		device pci 14.0 off end # xHCI Controller
+		device pci 1c.0 on # PCH PCIe Gen2 x4
+			# BCM56960 Switch ASIC
+		end
+		device pci 1d.0 on end # PCH EHCI Controller
+		device pci 1f.0 on # LPC
    		chip drivers/pc80/tpm
    			device pnp 0c31.0 on end
    		end
@@ -47,6 +63,9 @@
    	end # LPC Bridge
    	device pci 1f.2 on end # SATA Controller
    	device pci 1f.3 on end # SMBus Controller
-		device pci 1f.5 on end # SATA Controller
+		device pci 1f.5 off end # SATA Controller
+		device pci 1f.6 on # Thermal Management Controller
+			# DON'T DISABLE, CRASHES FSP MR2
+		end
    end
 end