Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33225 )
Change subject: soc/intel/braswell/smbus.c: Add support for i2c mode block write ......................................................................
Patch Set 14: Code-Review+1
(2 comments)
https://review.coreboot.org/#/c/33225/14/src/soc/intel/braswell/smbus.c File src/soc/intel/braswell/smbus.c:
https://review.coreboot.org/#/c/33225/14/src/soc/intel/braswell/smbus.c@49 PS14, Line 49: smbase = pci_read_config32(dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE; There is asymmetry in that the functions above use constant SMBUS_BASE_ADRESS and take (unused) smbus_dev argument. The big picture is, smbus prototypes are a mess in our tree...
https://review.coreboot.org/#/c/33225/14/src/soc/intel/braswell/smbus.c@53 PS14, Line 53: pci_write_config32(dev, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN); This should only be done after we know SMBUS host controller is not busy. I can live this, but this is really common to intel since ICH5 from what I know, and eventually needs refactorin and moving outside Braswell.