Attention is currently required from: Patrick Rudolph. Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52164 )
Change subject: soc/intel/xeon_sp: Set PCIE secure register lock ......................................................................
soc/intel/xeon_sp: Set PCIE secure register lock
Set PCIE SRL as indicated by the Intel documentation.
Change-Id: Ifa5bfb2824477b76ba34c3dc0588311f6c320092 Signed-off-by: Marc Jones marcjones@sysproconsulting.com --- M src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h M src/soc/intel/xeon_sp/lockdown.c 2 files changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/52164/1
diff --git a/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h b/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h index de7a73a..aff336b 100644 --- a/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h +++ b/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h @@ -42,6 +42,12 @@ #define SATAGC 0x9c #define SATAGC_REGLOCK BIT(31)
+#define PCH_DEV_SLOT_PCIE 0x1d +#define PCH_DEVFN_PCIE _PCH_DEVFN(PCIE, 0) +#define PCH_DEV_PCIE _PCH_DEV(PCIE, 0) +#define PCIE_MPC 0xd8 +#define SRL BIT(23) + #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) #define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index 0f032fc..d8c9b6a 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -44,9 +44,16 @@ } }
+static void pcie_lockdown_config(int chipset_lockdown) +{ + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) + pci_or_config32(PCH_DEV_PCIE, PCIE_MPC, SRL); +} + void soc_lockdown_config(int chipset_lockdown) { lpc_lockdown_config(chipset_lockdown); pmc_lockdown_config(chipset_lockdown); sata_lockdown_config(chipset_lockdown); + pcie_lockdown_config(chipset_lockdown); }