HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42191 )
Change subject: sb/intel/i82801gx: Use PCI bitwise ops ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42191/2/src/southbridge/intel/i8280... File src/southbridge/intel/i82801gx/azalia.c:
https://review.coreboot.org/c/coreboot/+/42191/2/src/southbridge/intel/i8280... PS2, Line 201: ~0x00ff0000 please why don't you keep it '0xff00ffff' ?
(same for all files)
https://review.coreboot.org/c/coreboot/+/42191/2/src/southbridge/intel/i8280... File src/southbridge/intel/i82801gx/pcie.c:
https://review.coreboot.org/c/coreboot/+/42191/2/src/southbridge/intel/i8280... PS2, Line 52: 0x0c please why 'PCI_CACHE_LINE_SIZE' is replaced by magic number ?