EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40415 )
Change subject: mb/google/puff: add a region to cache SPD data
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40415/4/src/mainboard/google/hatch/...
File src/mainboard/google/hatch/romstage_spd_smbus.c:
https://review.coreboot.org/c/coreboot/+/40415/4/src/mainboard/google/hatch/...
PS4, Line 40: get_spd_sn(blk.addr_map[i], SPD_DRAM_DDR4, sn);
Should dram type read from SPD? If hard code here, can't work on DDR3 right?
--
To view, visit
https://review.coreboot.org/c/coreboot/+/40415
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8d07fddf113a767d62394cb31e33b56f22f74351
Gerrit-Change-Number: 40415
Gerrit-PatchSet: 4
Gerrit-Owner: Jamie Chen
jamie.chen@intel.com
Gerrit-Reviewer: Edward O'Callaghan
quasisec@chromium.org
Gerrit-Reviewer: Furquan Shaikh
furquan@google.com
Gerrit-Reviewer: Kane Chen
kane.chen@intel.com
Gerrit-Reviewer: Tim Wawrzynczak
twawrzynczak@chromium.org
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Angel Pons
th3fanbus@gmail.com
Gerrit-CC: Arthur Heymans
arthur@aheymans.xyz
Gerrit-CC: EricR Lai
ericr_lai@compal.corp-partner.google.com
Gerrit-CC: Paul Menzel
paulepanter@users.sourceforge.net
Gerrit-Comment-Date: Tue, 28 Apr 2020 12:19:24 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment