Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39377 )
Change subject: amd/agesa/hudson: Disable `isa_dma_init()` ......................................................................
Patch Set 1:
Here is the failed log with `isa_dma_init()`. The changes are for enabling (commit hash and dirty).(Added debug prints showed, where it did not return from.)
``` coreboot-4.11-1492-geb0a992765-dirty Sat Mar 7 19:50:25 UTC 2020 bootblock starting (log level: 7)... FMAP: Found "FLASH" version 1.1 at 0x0. FMAP: base = 0xff800000 size = 0x800000 #areas = 3 FMAP: area COREBOOT found @ 200 (8388096 bytes) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 30000 size 4c36c BS: bootblock times (exec / console): total (unknown) / 16 ms
coreboot-4.11-1492-geb0a992765-dirty Sat Mar 7 19:50:25 UTC 2020 romstage starting (log level: 7)... APIC 00: CPU Family_Model = 00610f31
APIC 00: ** Enter AmdInitReset [00020007] Fch OEM config in INIT RESET PCI: 00:14.4 bridge ctrl <- 0013 PCI: 00:14.4 cmd <- 00 PCI: 00:14.5 cmd <- 02 PCI: 00:15.0 bridge ctrl <- 0013 PCI: 00:15.0 cmd <- 00 PCI: 00:15.1 bridge ctrl <- 0013 PCI: 00:15.1 cmd <- 06 PCI: 00:16.0 cmd <- 02 PCI: 00:16.2 cmd <- 02 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1022/1410 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/1410 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 subsystem <- 1022/1410 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/1410 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 subsystem <- 1022/1410 PCI: 00:18.5 cmd <- 00 PCI: 03:00.0 cmd <- ffff done. BS: BS_DEV_ENABLE run times (exec / console): 0 / 30 ms Initializing devices... Root Device init Root Device init finished in 0 msecs CPU_CLUSTER: 0 init start_eip=0x00001000, code_size=0x00000031 Initializing CPU #0 CPU: vendor AMD device 610f31 CPU: family 15, model 13, stepping 01 Model 15 Init.
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Enabling cache Setting up local APIC... apic_id: 0x10 done. siblings = 01, CPU #0 initialized Initializing CPU #1 Waiting for 1 CPUS to stop CPU: vendor AMD device 610f31 CPU: family 15, model 13, stepping 01 Model 15 Init.
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Enabling cache Setting up local APIC... apic_id: 0x11 done. siblings = 01, CPU #1 initialized All AP CPUs stopped (1060 loops) CPU_CLUSTER: 0 init finished in 40 msecs DOMAIN: 0000 init DOMAIN: 0000 init finished in 0 msecs PCI: 00:00.0 init PCI: 00:00.0 init finished in 0 msecs PCI: 00:01.0 init PCI: 00:01.0 init finished in 0 msecs PCI: 00:01.1 init PCI: 00:01.1 init finished in 0 msecs PCI: 00:11.0 init PCI: 00:11.0 init finished in 0 msecs PCI: 00:12.0 init PCI: 00:12.0 init finished in 0 msecs PCI: 00:12.2 init PCI: 00:12.2 init finished in 0 msecs PCI: 00:13.0 init PCI: 00:13.0 init finished in 0 msecs PCI: 00:13.2 init PCI: 00:13.2 init finished in 0 msecs PCI: 00:14.0 init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x04 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB PCI: 00:14.0 init finished in 7 msecs PCI: 00:14.2 init PCI: 00:14.2 init finished in 0 msecs PCI: 00:14.3 init ```