Chien-Chih Tseng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
WIP: soc/mediatek/mt8192: add apusys init flow
Signed-off-by: Chien-Chih Tseng chien-chih.tseng@mediatek.com Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/apusys.c A src/soc/mediatek/mt8192/include/soc/apusys.h M src/soc/mediatek/mt8192/soc.c 4 files changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48622/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc old mode 100644 new mode 100755 index c01d716..0b23296 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -54,6 +54,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += devapc.c ramstage-y += mcupm.c +ramstage-y += apusys.c ramstage-y += soc.c ramstage-y += sspm.c ramstage-y += ufs.c diff --git a/src/soc/mediatek/mt8192/apusys.c b/src/soc/mediatek/mt8192/apusys.c new file mode 100755 index 0000000..605f1c9 --- /dev/null +++ b/src/soc/mediatek/mt8192/apusys.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/apusys.h> +#include <soc/mtlib_common.h> + +#define INFRA2APU_SRAM_PROT_EN (INFRACFG_AO_BASE + 0xe98) +#define APUSYS_MBOX (0x19000000) + +void apusys_init(void) +{ + write32((void *)INFRA2APU_SRAM_PROT_EN, + read32((void *)INFRA2APU_SRAM_PROT_EN) & (~0xc0000000)); + write32((void *)(APUSYS_MBOX + 0x0b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x1b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x2b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x3b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x4b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x5b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x6b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x7b0), 0x00010001); + + printk(BIOS_INFO, "INFRA2APU_SRAM_PROT_EN = 0x%x\n", + read32((void *)INFRA2APU_SRAM_PROT_EN)); + printk(BIOS_INFO, "0x190000b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x0b0))); + printk(BIOS_INFO, "0x190001b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x1b0))); + printk(BIOS_INFO, "0x190002b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x2b0))); + printk(BIOS_INFO, "0x190003b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x3b0))); + printk(BIOS_INFO, "0x190004b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x4b0))); + printk(BIOS_INFO, "0x190005b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x5b0))); + printk(BIOS_INFO, "0x190006b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x6b0))); + printk(BIOS_INFO, "0x190007b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x7b0))); +} diff --git a/src/soc/mediatek/mt8192/include/soc/apusys.h b/src/soc/mediatek/mt8192/include/soc/apusys.h new file mode 100755 index 0000000..389d1e8 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/apusys.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_APUSYS_H +#define SOC_MEDIATEK_MT8192_APUSYS_H + +#include <soc/addressmap.h> +#include <types.h> + +void apusys_init(void); +#endif /* SOC_MEDIATEK_MT8192_APUSYS_H */ diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c old mode 100644 new mode 100755 index 883f4dc..8c16906 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -4,10 +4,12 @@ #include <soc/devapc.h> #include <soc/emi.h> #include <soc/mcupm.h> +#include <soc/apusys.h> #include <soc/mmu_operations.h> #include <soc/sspm.h> #include <soc/ufs.h> #include <symbols.h> +#include <console/console.h>
static void soc_read_resources(struct device *dev) { @@ -17,6 +19,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + apusys_init(); dapc_init(); mcupm_init(); sspm_init();