[coreboot-gerrit] Change in coreboot[master]: ec/google/chromeec: Add SSDT generator for ChromeOS EC

[Tim Wawrzynczak (Code Review)]

Hello Duncan Laurie, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38541

to look at the new patch set (#15).

Change subject: ec/google/chromeec: Add SSDT generator for ChromeOS EC
......................................................................

ec/google/chromeec: Add SSDT generator for ChromeOS EC

Upcoming versions of the Linux kernel (5.5.1) would like to consume
information about the USB PD ports that are attached to the device. This
information is obtained from the CrOS EC and exposed in the SSDT ACPI
table.

Also, the device enable for this PCI device is moved from ec_lpc.c to
a new file, ec_chip.c, where EC-related ACPI methods can live.  It
still allows other code to call functions on device enable (so that
PnP enable for the LPC device still gets called).

BUG=b:146506369
BRANCH=none
TEST=Verify the SSDT contains the expected information

Change-Id: I729caecd64d9320fb02c0404c8315122f010970b
Signed-off-by: Tim Wawrzynczak 
---
M src/ec/google/chromeec/Makefile.inc
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec.h
A src/ec/google/chromeec/ec_chip.c
M src/ec/google/chromeec/ec_lpc.c
5 files changed, 259 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38541/15