[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update PMC Register Base and platform check for JSP

[Usha P (Code Review)]

Hello Patrick Rudolph, Karthik Ramasubramanian, Subrata Banik, Sridhar Siricilla, Meera Ravindranath, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38704

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Update PMC Register Base and platform check for JSP
......................................................................

soc/intel/tigerlake: Update PMC Register Base and platform check for JSP

Change:
    1. PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP to 0X0A00 for JSP
    2. Platform check in espi.c

BUG=None
TEST=
    1. Test for JSL RVP Boot
    2. Verify PMC register values are valid for GEN_PMCON
       and GBLRST_CAUSE

Change-Id: I6017a9703764b5454e7be479c1e08afe614908f1
Signed-off-by: Usha P 
Signed-off-by: Meera Ravindranath 
---
M src/soc/intel/tigerlake/bootblock/pch.c
M src/soc/intel/tigerlake/espi.c
2 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/38704/2