Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config
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Patch Set 20:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ro...
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ro...
PS20, Line 148: pcie_rp_init
nit: I think it would be good to align this one more tab or basically move this to the previous line and anything that overflows the column limit can be moved to this line.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Gerrit-Change-Number: 48340
Gerrit-PatchSet: 20
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