Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39166 )
Change subject: mb/google/dedede: Add PCIe Root Port Configuration ......................................................................
mb/google/dedede: Add PCIe Root Port Configuration
Add configuration for all the PCIe Root ports and Clock Source. Configure the Root Ports as disabled and clock sources as not used.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39166/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index d5f58ba..bbd7642 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -76,6 +76,30 @@ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }"
+ # PCIE Root Port Configuration + register "PcieRpEnable[0]" = "0" + register "PcieRpEnable[1]" = "0" + register "PcieRpEnable[2]" = "0" + register "PcieRpEnable[3]" = "0" + register "PcieRpEnable[4]" = "0" + register "PcieRpEnable[5]" = "0" + register "PcieRpEnable[6]" = "0" + register "PcieRpEnable[7]" = "0" + + register "PcieClkSrcUsage[0]" = "0xff" + register "PcieClkSrcUsage[1]" = "0xff" + register "PcieClkSrcUsage[2]" = "0xff" + register "PcieClkSrcUsage[3]" = "0xff" + register "PcieClkSrcUsage[4]" = "0xff" + register "PcieClkSrcUsage[5]" = "0xff" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "0" + register "PcieClkSrcClkReq[2]" = "0" + register "PcieClkSrcClkReq[3]" = "0" + register "PcieClkSrcClkReq[4]" = "0" + register "PcieClkSrcClkReq[5]" = "0" + # Enable EMMC HS400 mode register "ScsEmmcHs400Enabled" = "1"