[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update PMC Register Base for JSP

[Usha P (Code Review)]

Hello Meera Ravindranath,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/38704

to review the following change.

Change subject: soc/intel/tigerlake: Update PMC Register Base for JSP
......................................................................

soc/intel/tigerlake: Update PMC Register Base for JSP

Update PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP to 0X0A00 for JSP

BUG=None
TEST=
    1. Test for JSL RVP Boot
    2. Verify PMC register values are valid for GEN_PMCON
       and GBLRST_CAUSE

Change-Id: I6017a9703764b5454e7be479c1e08afe614908f1
Signed-off-by: Usha P 
Signed-off-by: Meera Ravindranath 
---
M src/soc/intel/tigerlake/bootblock/pch.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/38704/1

diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 1654809..6e7393a 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -41,7 +41,7 @@
 #include <soc/pm.h>

#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP	0x1100
-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP	0x0980
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP	0x0A00
 #define PCR_PSFX_TO_SHDW_BAR0	0
 #define PCR_PSFX_TO_SHDW_BAR1	0x4
 #define PCR_PSFX_TO_SHDW_BAR2	0x8