Scott Radcliffe (sradcliffe@microind.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7039
-gerrit
commit 727e3583553614c7c1d4860f34011d66905c2259 Author: Scott Radcliffe sradcliffe@microind.com Date: Fri Oct 10 16:15:01 2014 -0400
baytrail: Add padding to the end of device_nvs to match ACPI
ACPI globalnvs.asl expects the gnvs memory area size to be 0x2000. Padding has been added to device_nvs struct to reserve the full 0x2000 bytes for gnvs usage.
No known issues are caused by having the GNVS area shorter than what ACPI thinks. Since there's nothing defined in this area, O/S shouldn't try to access it. Only problem might be if O/S notices the SSDT is located within the GNVS defined area.
I verified that the next table written to memory (SSDT) is 0x2000 past GNVS start using a custom-designed Baytrail-I motherboard based on the Intel Bayley Bay CRB.
Change-Id: I9792954c7a3403eba6f37d7e53ea4a9ed3a2e4ac Signed-off-by: Scott Radcliffe sradcliffe@microind.com --- src/soc/intel/baytrail/baytrail/device_nvs.h | 3 ++- src/soc/intel/fsp_baytrail/baytrail/device_nvs.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/baytrail/baytrail/device_nvs.h b/src/soc/intel/baytrail/baytrail/device_nvs.h index f8f831b..c7fbc45 100644 --- a/src/soc/intel/baytrail/baytrail/device_nvs.h +++ b/src/soc/intel/baytrail/baytrail/device_nvs.h @@ -55,13 +55,14 @@ typedef struct { u32 scc_bar0[3]; u32 lpe_bar0;
- /* BAR 0 */ + /* BAR 1 */ u32 lpss_bar1[14]; u32 scc_bar1[3]; u32 lpe_bar1;
/* Extra */ u32 lpe_fw; /* LPE Firmware */ + u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ } __attribute__((packed)) device_nvs_t;
#endif diff --git a/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h b/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h index a06ca70..1ed897f 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h +++ b/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h @@ -55,13 +55,14 @@ typedef struct { u32 scc_bar0[3]; u32 lpe_bar0;
- /* BAR 1 */ + /* BAR 0 */ u32 lpss_bar1[14]; u32 scc_bar1[3]; u32 lpe_bar1;
/* Extra */ u32 lpe_fw; /* LPE Firmware */ + u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ } __attribute__((packed)) device_nvs_t;
#endif