[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Check TBT & TCSS ports for wake events

[Tim Wawrzynczak (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Caveh Jalali, Nick Vaccaro, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47396

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Check TBT & TCSS ports for wake events
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soc/intel/tigerlake: Check TBT & TCSS ports for wake events

Wakes from TBT ports and TCSS devices will show up as PME_B0_STS wakes,
so add checks for wakes from these devices in
pch_log_pme_internal_wake_source.

Signed-off-by: Tim Wawrzynczak 
Change-Id: Ie9904c3c01ea85fcd83218fcfeaa4378b07c1463
---
M src/soc/intel/tigerlake/elog.c
M src/soc/intel/tigerlake/xhci.c
2 files changed, 62 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/47396/3