Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16202
-gerrit
commit eec4c8e19cf0cc08d2d8c7363d172d6ec9ad7da7 Author: Aaron Durbin adurbin@chromium.org Date: Thu Aug 11 23:55:39 2016 -0500
soc/intel/skylake: use SPI flash boot_device_rw() for ealy stages
If the boot device is SPI flash use use the common one in the early stages. While tweaking the config don't auto select SPI_FLASH as that is handled automatically by the rest of the build system.
BUG=chrome-os-partner:56151
Change-Id: Ifd51a80fd008c336233d6e460c354190fcc0ef22 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/soc/intel/skylake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 909dcec..f13c84e 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select ACPI_NHLT + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE @@ -46,7 +47,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select SMM_TSEG select SMP - select SPI_FLASH select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_CONSTANT_RATE