[coreboot-gerrit] Change in coreboot[master]: arch/riscv: Only execute on hart 0 for now

[Philipp Hug (Code Review)]

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28605

Change subject: arch/riscv: Only execute on hart 0 for now
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arch/riscv: Only execute on hart 0 for now

Only execute coreboot on hart 0 until synchronisation between hart's is ready.
Change-Id: I2181e79572fbb9cc7bee39a3c2298c0dae6c1658
Signed-off-by: Philipp Hug 
---
M src/arch/riscv/bootblock.S
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/28605/1

diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index 81a4455..95e1923 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -24,6 +24,12 @@
 .global _estack
 .globl _start
 _start:
+	csrr a0, mhartid
+	li a3, 0
+	beq a0, a3, _hart_zero
+_hart_loop:
+	j _hart_loop
+_hart_zero:

# The boot ROM may pass the following arguments to coreboot:
    #   a0: the value of mhartid