Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41903 )
Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP WW22 release ......................................................................
vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP WW22 release
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I70762b377a057d0fca7806f485cce8d479fb5baa --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 3 files changed, 52 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/41903/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index c4c23df..a5175e8 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -481,57 +481,76 @@ **/ UINT8 KtiInEnableMktme;
-/** Offset 0x00CF -**/ - UINT8 UnusedUpdSpace4; - -/** Offset 0x00D0 - Address of IIoBifurcationTable. - The address of the table of IIoBifurcation. +/** Offset 0x00CF - IIO ConfigIOU0 + ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO $EN_DIS **/ - UINT32 IIoBifurcationTablePtr; + UINT8 IioConfigIOU0[8];
-/** Offset 0x00D4 - Number of IIoBifurcationTable Entry - Number of IIoBifurcationTable Entry. If this is not zero, the IIoBifurcationTablePtr - must not be NULL. +/** Offset 0x00D7 - IIO ConfigIOU1 + ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ - UINT8 NumOfIIoBifurcationTable; + UINT8 IioConfigIOU1[8];
-/** Offset 0x00D5 - PchAdrEn +/** Offset 0x00DF - IIO ConfigIOU2 + ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO +**/ + UINT8 IioConfigIOU2[8]; + +/** Offset 0x00E7 - IIO ConfigIOU3 + ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO +**/ + UINT8 IioConfigIOU3[8]; + +/** Offset 0x00EF - IIO ConfigIOU4 + ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO +**/ + UINT8 IioConfigIOU4[8]; + +/** Offset 0x00F7 - PchAdrEn Enable or Disable PchAdr **/ UINT8 PchAdrEn;
-/** Offset 0x00D6 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00F8 - } TYPE:{Combo + Root port swapping based on device connection status : TRUE or FALSE + TRUE : 0x01, FALSE : 0x00 **/ UINT8 PchPcieRootPortFunctionSwap;
-/** Offset 0x00D7 - PCH PCIE PLL Ssc +/** Offset 0x00F9 - PCH PCIE PLL Ssc Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF **/ UINT8 PchPciePllSsc;
-/** Offset 0x00D8 - Usage type for PCH PCIE Root Port Index +/** Offset 0x00FA - Usage type for PCH PCIE Root Port Index Index assigned to every PCH PCIE Root Port **/ UINT8 PchPciePortIndex[20];
-/** Offset 0x00EC - Usage type for PCH PCIE Root Port Enable or Disable - 0-19: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use - (free running), 0xFF: not used +/** Offset 0x010E - Usage type for PCH PCIE Root Port Enable or Disable + 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, + the value is 0x00 **/ UINT8 PchPcieForceEnable[20];
-/** Offset 0x0100 - Usage type for PCH PCIE Root Port Link Speed - 0-19: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use - (free running), 0xFF: not used +/** Offset 0x0122 - Usage type for PCH PCIE Root Port Link Speed + 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie + Gen2 Speed, 0x03 : Pcie Gen3 Speed **/ UINT8 PchPciePortLinkSpeed[20];
-/** Offset 0x0114 +/** Offset 0x0136 +**/ + UINT8 UnusedUpdSpace4[2]; + +/** Offset 0x0138 **/ UINT8 ReservedMemoryInitUpd[16]; } FSP_M_CONFIG; @@ -552,11 +571,11 @@ **/ FSP_M_CONFIG FspmConfig;
-/** Offset 0x0124 +/** Offset 0x0148 **/ - UINT8 UnusedUpdSpace5[2]; + UINT8 UnusedUpdSpace5[6];
-/** Offset 0x0126 +/** Offset 0x014E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 1ce5d30..7ac630f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -273,7 +273,6 @@ uint8_t DmiVc1; uint8_t DmiVcm; uint32_t CpuPCPSInfo; - uint8_t LtsxEnable; uint8_t MctpEn; uint8_t cpuSubType; uint8_t SystemRasType; diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 6b0823c..e9c7dbf 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -99,7 +99,12 @@ UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES];
- UINT8 reserved3[24409]; + UINT8 reserved3[24417]; + + UINT32 MmiohBase; // MMIOH base in 64MB granularity + + UINT8 reserved4[10]; + } SYSTEM_MEMORY_MAP_HOB;
#pragma pack()