shkim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34397/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34397/1//COMMIT_MSG@10 PS1, Line 10: The main perpose of this change is adjusting PL1, and we need further fine tuning later.
Please wrap the line.
Done
https://review.coreboot.org/c/coreboot/+/34397/1//COMMIT_MSG@10 PS1, Line 10: perpose
purpose
Done
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... PS1, Line 63: 51000
Any reason for keeping PowerLimit Minimum and Maximum (below) to same value 51W ?
As I know PL2 setting in DPTF table doesn't work. DUT just sets PL2 with "tdp_pl2_override" value and chrome DPTF does not change PL2 value in runtime. I changed this to just indicate current setting. Please let me know if I have misunderstanding.
PL2 51W is recommended value for CML-U system with 8W TDP design. I got this value from a document from Intel (I don't remember what it was exactly, but we used this value in TPnP camp; b:136138567).
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... PS1, Line 64: 51000
Shouldn't this match tdp_pl2_override? That seems to be set to 52W and not 51W here: https://review. […]
Done