Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40363 )
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40363/1/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/Kconfig:
https://review.coreboot.org/c/coreboot/+/40363/1/src/soc/intel/common/block/... PS1, Line 18: default 0x100 if (PCIEX_LENGTH_256MB) : default 0x80 if (PCIEX_LENGTH_128MB) : default 0x40 if (PCIEX_LENGTH_64MB) : default 0x100 this changes should have gone into CB:40235 itself
https://review.coreboot.org/c/coreboot/+/40363/1/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent_early.c:
https://review.coreboot.org/c/coreboot/+/40363/1/src/soc/intel/common/block/... PS1, Line 47: case 256: : pciexbar_length = PCIEXBAR_LENGTH_256MB; : break; : case 128: : pciexbar_length = PCIEXBAR_LENGTH_128MB; : break; : case 64: : pciexbar_length = PCIEXBAR_LENGTH_64MB; : break; this changes should have gone into CB:40235 itself