Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2920
-gerrit
commit 86e82bfb4879f7e45312bffd08a06b48ef08b897 Author: Aaron Durbin adurbin@chromium.org Date: Tue Mar 26 13:34:37 2013 -0500
libpayload: add x86 ROM variable MTRR support
On x86, Coreboot may allocate a variable range MTRR for enabling caching of the system ROM. Add the ability to parse this structure and add the result to the sysinfo structure.
Change-Id: I3bfe2028d8574d3adb1d85292abf8f1372cf97fa Signed-off-by: Aaron Durbin adurbin@chromium.org --- payloads/libpayload/arch/x86/coreboot.c | 23 ++++++++++++++++++++++- payloads/libpayload/include/coreboot_tables.h | 12 ++++++++++++ payloads/libpayload/include/sysinfo.h | 5 +++++ 3 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index f4f9b86..77e094f 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -158,6 +158,14 @@ static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) } #endif
+#if CONFIG_ARCH_X86 +static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info) +{ + struct cb_x86_rom_mtrr *rom_mtrr = ptr; + info->x86_rom_var_mtrr_index = index; +} +#endif + static void cb_parse_string(unsigned char *ptr, char **info) { *info = (char *)((struct cb_string *)ptr)->string; @@ -281,6 +289,11 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_MRC_CACHE: cb_parse_mrc_cache(ptr, info); break; +#if CONFIG_ARCH_X86 + case CB_TAG_X86_ROM_MTRR: + cb_parse_x86_rom_var_mtrr(ptr, info); + break; +#endif }
ptr += rec->size; @@ -294,7 +307,15 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info); + int ret; + +#if CONFIG_ARCH_X86 + /* Ensure the variable range MTRR index covering the ROM is set to + * an invalid value. */ + info->x86_rom_var_mtrr_index = -1; +#endif + + ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
if (ret != 1) ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info); diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 38bda55..02c9449 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -217,6 +217,18 @@ struct cb_vboot_handoff { uint32_t vboot_handoff_size; };
+#define CB_TAG_X86_ROM_MTRR 0x0021 +struct cb_x86_rom_mtrr { + uint32_t tag; + uint32_t size; + /* The variable range MTRR index covering the ROM. If one wants to + * enable caching the ROM, the variable MTRR needs to be set to + * write-protect. To disable the caching after enabling set the + * type to uncacheable. */ + uint32_t index; +}; + + #define CB_TAG_CMOS_OPTION_TABLE 0x00c8 struct cb_cmos_option_table { u32 tag; diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index e05ef9f..a4afd01 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -99,6 +99,11 @@ struct sysinfo_t { void *vdat_addr; u32 vdat_size; #endif + +#ifdef CONFIG_ARCH_X86 + long x86_rom_var_mtrr_index; +#endif + void *tstamp_table; void *cbmem_cons; void *mrc_cache;