Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )
Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37168/5/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/37168/5/src/southbridge/amd/agesa/h... PS5, Line 20: ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) We should make the build work without this guard, I'll have a look.
https://review.coreboot.org/c/coreboot/+/37168/5/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/early_setup.c:
https://review.coreboot.org/c/coreboot/+/37168/5/src/southbridge/amd/agesa/h... PS5, Line 108: | DECODE_ENABLE_ADLIB_PORT; The choice made on Intel side was to only open LPC routes for the required devices.