[coreboot-gerrit] Change in coreboot[master]: arch/x86/riscv: Don't link `stages.c` into ramstage

[Nico Huber (Code Review)]

Hello Arthur Heymans, Jonathan Neuschäfer, Philipp Hug,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/36610

to review the following change.

Change subject: arch/x86/riscv: Don't link `stages.c` into ramstage
......................................................................

arch/x86/riscv: Don't link `stages.c` into ramstage

It's superseded by `ramstage.S`.

Change-Id: I81648da2f2af3ad73b3b51471c6fa2daac0540b1
Signed-off-by: Nico Huber 
---
M src/arch/riscv/Makefile.inc
1 file changed, 0 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/36610/1

diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 0039fab..16f160e 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -140,7 +140,6 @@
 ramstage-y += misaligned.c
 ramstage-y += sbi.c
 ramstage-y += virtual_memory.c
-ramstage-y += stages.c
 ramstage-y += misc.c
 ramstage-y += smp.c
 ramstage-y += boot.c