[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8192: Reserved 44K SRAM for mcupm working buffer

[Yidi Lin (Code Review)]

Hello CK HU,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/46401

to review the following change.

Change subject: soc/mediatek/mt8192: Reserved 44K SRAM for mcupm working buffer
......................................................................

soc/mediatek/mt8192: Reserved 44K SRAM for mcupm working buffer

Reserved region is 0x00115000 ~ 0x0011ffff and reduce
PRERAM_CBMEM_CONSOLE buffer from 63K to 19K.

Signed-off-by: CK Hu 
Change-Id: Ic82a194736eecd7bdc8df80b493290090a2ccba5
---
M src/soc/mediatek/mt8192/include/soc/memlayout.ld
1 file changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/46401/1

diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
index 3bef5b1..20aa431 100644
--- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
@@ -21,12 +21,12 @@
    TPM_TCPA_LOG(0x00103000, 2K)
    FMAP_CACHE(0x00103800, 2K)
    WATCHDOG_TOMBSTONE(0x00104000, 4)
-	PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4)
-	TIMESTAMP(0x00113c00, 1K)
-	STACK(0x00114000, 16K)
-	TTB(0x00118000, 28K)
-	DMA_COHERENT(0x0011f000, 4K)
-	SRAM_END(0x00120000)
+	PRERAM_CBMEM_CONSOLE(0x00104004, 19K - 4)
+	TIMESTAMP(0x00108c00, 1K)
+	STACK(0x00109000, 16K)
+	TTB(0x0010d000, 28K)
+	DMA_COHERENT(0x00114000, 4K)
+	SRAM_END(0x00115000)

SRAM_L2C_START(0x00200000)
    BOOTBLOCK(0x00201000, 64K)