Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 22:
(6 comments)
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 135: /* Need to update DLL setting to get Emmc running at HS400 speed */ : uint8_t EmmcUseCustomDlls; : uint32_t EmmcTxCmdDelayRegValue; : uint32_t EmmcTxDataDelay1RegValue; : uint32_t EmmcTxDataDelay2RegValue; : uint32_t EmmcRxCmdDataDelay1RegValue; : uint32_t EmmcRxCmdDataDelay2RegValue; : uint32_t EmmcRxStrobeDelayRegValue;
Yes, we can use the DLL params from soc_intel_common. […]
Ack
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 145: SdCardPowerEnableActiveHigh
This is not added but it just keep the chip. […]
Ack
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 70: PlatformMemorySize
But, I don't see any code actually utilizing this.
We provide though UPD but will use FSP default value: Delete
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 73: TsegSize
FSP UPD is set to CONFIG_SMM_TSEG_SIZE. So, this should not be required.
Ack
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 123: CONFIG_MAX_ROOT_PORTS
As far as I can see, this is the same for TGL and JSL. […]
Use CONFIG_MAX_PCIE_CLOCKS
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 126: CONFIG_MAX_ROOT_PORTS
Same here.
Use CONFIG_MAX_PCIE_CLOCKS