[coreboot-gerrit] Change in coreboot[master]: mb/google/asurada: change EC SPI to 3M

[Yidi Lin (Code Review)]

Hello Hung-Te Lin,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/46394

to review the following change.

Change subject: mb/google/asurada: change EC SPI to 3M
......................................................................

mb/google/asurada: change EC SPI to 3M

To prevent timeout on long EC packet, we should increase EC SPI speed to
the same value that kernel is using (3M).

BUG=b:161509047
TEST=emerge-asurada coreboot chromeos-bootimage; flash and boot

Change-Id: I9c47324022129ca23ef75d0c80e215da1692636d
---
M src/mainboard/google/asurada/bootblock.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/46394/1

diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c
index 04e8898..647555a 100644
--- a/src/mainboard/google/asurada/bootblock.c
+++ b/src/mainboard/google/asurada/bootblock.c
@@ -7,7 +7,7 @@

void bootblock_mainboard_init(void)
 {
-	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
+	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
    mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
    setup_chromeos_gpios();
    gpio_eint_configure(GPIO_H1_AP_INT, IRQ_TYPE_EDGE_RISING);