[coreboot-gerrit] Change in coreboot[master]: mb/intel/kblrvp8:[WIP] Add KBLRVP8 support

[V Sowmya (Code Review)]

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/25194

Change subject: mb/intel/kblrvp8:[WIP] Add KBLRVP8 support
......................................................................

mb/intel/kblrvp8:[WIP] Add KBLRVP8 support

Add the config for setting SPD DIMM size to 512 bytes
for KBLRVP8 with DDR4 memory. Configure the channel 1
DIMM0 and DIMM1 memory SPD data. Set the UserBd UPD to
BOARD_TYPE_DESKTOP.

Signed-off-by: V Sowmya 
Change-Id: I985968d331991884050c3920ec9798cd4cb371c7
---
M src/mainboard/intel/kblrvp/Kconfig
M src/mainboard/intel/kblrvp/romstage.c
2 files changed, 12 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/25194/1

diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
index 5ca46e1..bbeb129 100644
--- a/src/mainboard/intel/kblrvp/Kconfig
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -98,4 +98,7 @@
    hex
    default 0xd00

+config DIMM_SPD_SIZE
+	int
+	default 512 if BOARD_INTEL_KBLRVP8 #DDR4
 endif
diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c
index 7bfbe1c..558c0be 100644
--- a/src/mainboard/intel/kblrvp/romstage.c
+++ b/src/mainboard/intel/kblrvp/romstage.c
@@ -49,7 +49,7 @@
    	mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);
    	/* Memory leak is ok since we have memory mapped boot media */
    	mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
-	} else {  /* for CONFIG_BOARD_INTEL_KBLRVP7 */
+	} else { /* CONFIG_BOARD_INTEL_KBLRVP7 and CONFIG_BOARD_INTEL_KBLRVP8*/
    	struct spd_block blk = {
    		.addr_map = { 0x50, 0x51, 0x52, 0x53, },
    	};
@@ -58,8 +58,14 @@
    	get_spd_smbus(&blk);
    	mem_cfg->MemorySpdDataLen = blk.len;
    	mem_cfg->MemorySpdPtr00 = (u32)blk.spd_array[0];
-	}
-	mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+		mem_cfg->MemorySpdPtr01 = (u32)blk.spd_array[1];
+		if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) {
+			mem_cfg->MemorySpdPtr10 = (u32)blk.spd_array[2];
+			mem_cfg->MemorySpdPtr11 = (u32)blk.spd_array[3];
+		}

+	}
    mupd->FspmTestConfig.DmiVc1 = 1;
+	if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8))
+		mem_cfg->UserBd = BOARD_TYPE_DESKTOP;
 }