[coreboot-gerrit] Change in coreboot[master]: mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv config

[PraveenX Hodagatta Pranesh (Code Review)]

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36423 )

Change subject: mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv config
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mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv config

Change-Id: Ia31da9997ba46c15cd385bf55e009cf299848b64
Signed-off-by: Praveen Hodagatta Pranesh 
---
M src/mainboard/intel/kunimitsu/devicetree.cb
M src/mainboard/intel/saddlebrook/devicetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/36423/1

diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 670a474..ea35785 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -34,7 +34,7 @@
    register "SkipExtGfxScan" = "1"
    register "Device4Enable" = "1"
    register "HeciEnabled" = "0"
-	register "SaGv" = "3"
+	register "SaGv" = "SaGv_Enabled"
    register "PmTimerDisabled" = "1"

register "pirqa_routing" = "PCH_IRQ11"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 385a4be..22013bf 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -43,7 +43,7 @@
    register "Device4Enable" = "0"
    register "Heci3Enabled" = "0"

-	register "SaGv" = "3"
+	register "SaGv" = "SaGv_Enabled"
    register "PmTimerDisabled" = "0"

# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch