[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update FSP params for Jasper Lake

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded a new patch set (#25) to the change originally created by Maulik V Vaghela. ( https://review.coreboot.org/c/coreboot/+/38461 )

Change subject: soc/intel/tigerlake: Update FSP params for Jasper Lake
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soc/intel/tigerlake: Update FSP params for Jasper Lake

Update FSP parameters for various configurations like:
- graphics
- USB
- PCIe root ports
- SD card
- eMMC
- Audio
- Basic UART configuration

These are the initial settings for JSL.

This patch also corrects the debug_interface_flag definitions.

TEST=Build dedede board

Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb
Signed-off-by: Maulik V Vaghela 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_jsl.c
M src/soc/intel/tigerlake/include/soc/pci_devs.h
M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
5 files changed, 265 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/38461/25