[coreboot-gerrit] Change in coreboot[master]: mb/tglrvp: Update SPD files for Hynex

[Anil Kumar K (Code Review)]

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44149 )

Change subject: mb/tglrvp: Update SPD files for Hynex
......................................................................

mb/tglrvp: Update SPD files for Hynex

- Increase DDR Frquency limit to support data rate 4266 Mbps

Bug=None
Test=Build and boot on tglrvp hardware;
     $dmidecode --type 17 reflects memory Speed = 4266

Signed-off-by: Anil Kumar 
Change-Id: I8185ebbaa32a01fee104bc0b757fc4adb58bba97
---
M src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/44149/1

diff --git a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex
index 2ff9ed3..4bf724e 100644
--- a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex
+++ b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex
@@ -1,5 +1,5 @@
 23 11 11 0E 1B 21 F9 08 00 40 00 00 0A 01 00 00
-00 00 05 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60
+00 00 04 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00