[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: remove warm reset flag code

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55101 )

Change subject: soc/amd/cezanne: remove warm reset flag code
......................................................................

soc/amd/cezanne: remove warm reset flag code

The warm reset bit in the NCP_ERR register doesn't behave as the PPR [1]
suggested; no matter if something was written to the register, the
NCP_WARM_BOOT bit never got set and the NCP_ERR register in I/O-space
always reads back as 0x7f.

[1] checked with PPR for AMD Family 19h Model 51h A1 (CZN) #56569 Rev
3.01

Signed-off-by: Felix Held 
Change-Id: I569372db9f36ec7bbc741f4d7312ade312daa70b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55101
Reviewed-by: Raul Rangel 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/cezanne/cpu.c
M src/soc/amd/cezanne/include/soc/iomap.h
M src/soc/amd/cezanne/include/soc/southbridge.h
M src/soc/amd/cezanne/reset.c
4 files changed, 0 insertions(+), 19 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index f002665..ddc49a9 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -55,8 +55,6 @@

/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
    mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
-
-	set_warm_reset_flag();
 }

static void zen_2_3_init(struct device *dev)
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h
index 4c4252a..4f01c64 100644
--- a/src/soc/amd/cezanne/include/soc/iomap.h
+++ b/src/soc/amd/cezanne/include/soc/iomap.h
@@ -44,7 +44,6 @@
 #endif /* ENV_X86 */

/* I/O Ranges */
-#define NCP_ERR				0x00f0
 #define ACPI_IO_BASE			0x0400
 #define  ACPI_PM_EVT_BLK		(ACPI_IO_BASE + 0x00)
 #define   ACPI_PM1_STS			(ACPI_PM_EVT_BLK + 0x00)
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index e58a8cd..e82f33f 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -118,9 +118,6 @@
 #define FCH_AOAC_DEV_AMBA		17
 #define FCH_AOAC_DEV_ESPI		27

-/* IO 0xf0 NCP Error */
-#define   NCP_WARM_BOOT			(1 << 7) /* Write-once */
-
 void fch_pre_init(void);
 void fch_early_init(void);
 void fch_init(void *chip_info);
diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/cezanne/reset.c
index b05c0b6..1360bd5 100644
--- a/src/soc/amd/cezanne/reset.c
+++ b/src/soc/amd/cezanne/reset.c
@@ -7,19 +7,6 @@
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/reset.h>

-/* TODO: is NCP_ERR still valid?  It appears reserved and always 0xff.  b/184281092 */
-void set_warm_reset_flag(void)
-{
-	uint8_t ncp = inb(NCP_ERR);
-
-	outb(NCP_ERR, ncp | NCP_WARM_BOOT);
-}
-
-int is_warm_reset(void)
-{
-	return !!(inb(NCP_ERR) & NCP_WARM_BOOT);
-}
-
 void do_cold_reset(void)
 {
    /* De-assert and then assert all PwrGood signals on CF9 reset. */