Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4615
-gerrit
commit 73efb597c7671a0425d8fc057ff10fd6762a3605 Author: Vladimir Serbinenko phcoder@gmail.com Date: Sun Jan 5 06:40:36 2014 +0100
ROMSIZE: Add option for 12M chips.
On X230 2 real chips (8 + 4) are merged into one virtual 12M chip.
Change-Id: I04e676e4a0a5b074d8a45dbfa8a595629fd1b66d Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/cpu/intel/haswell/romstage.c | 4 ++-- src/cpu/x86/Kconfig | 2 +- src/cpu/x86/mtrr/mtrr.c | 4 ++-- src/mainboard/Kconfig | 23 +++++++++++++++++++++++ src/mainboard/amd/dinar/agesawrapper.c | 4 ++-- src/mainboard/amd/inagua/romstage.c | 4 ++-- src/mainboard/amd/olivehill/agesawrapper.c | 4 ++-- src/mainboard/amd/parmer/agesawrapper.c | 4 ++-- src/mainboard/amd/persimmon/romstage.c | 4 ++-- src/mainboard/amd/south_station/romstage.c | 4 ++-- src/mainboard/amd/thatcher/agesawrapper.c | 4 ++-- src/mainboard/amd/torpedo/agesawrapper.c | 4 ++-- src/mainboard/amd/union_station/romstage.c | 4 ++-- src/mainboard/asrock/e350m1/romstage.c | 4 ++-- src/mainboard/asrock/imb-a180/agesawrapper.c | 4 ++-- src/mainboard/asus/f2a85-m/agesawrapper.c | 4 ++-- src/mainboard/gizmosphere/gizmo/romstage.c | 8 ++++---- src/mainboard/lippert/frontrunner-af/romstage.c | 4 ++-- src/mainboard/lippert/toucan-af/romstage.c | 4 ++-- src/mainboard/supermicro/h8qgi/agesawrapper.c | 4 ++-- src/mainboard/supermicro/h8scm/agesawrapper.c | 4 ++-- src/mainboard/tyan/s8226/agesawrapper.c | 4 ++-- 22 files changed, 66 insertions(+), 43 deletions(-)
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 35b51c5..ea63ef8 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -124,9 +124,9 @@ static void *setup_romstage_stack_after_car(void)
/* Cache the ROM as WP just below 4GiB. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); + slot = stack_push(slot, ~(CONFIG_ALIGNED_ROM_SIZE - 1) | MTRRphysMaskValid); slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); + slot = stack_push(slot, ~(CONFIG_ALIGNED_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); num_mtrrs++;
/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index c64a8e4..f509786 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -65,7 +65,7 @@ config TSC_SYNC_MFENCE
config XIP_ROM_SIZE hex - default ROM_SIZE if ROMCC + default ALIGNED_ROM_SIZE if ROMCC default 0x10000
config CPU_ADDR_BITS diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d168978..955cec7 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -190,8 +190,8 @@ static struct memranges *get_physical_address_space(void) * when CONFIG_CACHE_ROM is enabled. The ROM is assumed * to be located at 4GiB - rom size. */ resource_t rom_base = RANGE_TO_PHYS_ADDR( - RANGE_4GB - PHYS_TO_RANGE_ADDR(CONFIG_ROM_SIZE)); - memranges_insert(addr_space, rom_base, CONFIG_ROM_SIZE, + RANGE_4GB - PHYS_TO_RANGE_ADDR(CONFIG_ALIGNED_ROM_SIZE)); + memranges_insert(addr_space, rom_base, CONFIG_ALIGNED_ROM_SIZE, MTRR_TYPE_WRPROT); #endif
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 1e8d98f..7c5683b 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -228,6 +228,8 @@ config BOARD_ROMSIZE_KB_4096 bool config BOARD_ROMSIZE_KB_8192 bool +config BOARD_ROMSIZE_KB_12288 + bool config BOARD_ROMSIZE_KB_16384 bool
@@ -242,6 +244,7 @@ choice default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 + default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 default COREBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 help Select the size of the ROM chip you intend to flash coreboot on. @@ -289,6 +292,11 @@ config COREBOOT_ROMSIZE_KB_8192 help Choose this option if you have a 8192 KB (8 MB) ROM chip.
+config COREBOOT_ROMSIZE_KB_12288 + bool "12288 KB (12 MB)" + help + Choose this option if you have a 12288 KB (12 MB) ROM chip. + config COREBOOT_ROMSIZE_KB_16384 bool "16384 KB (16 MB)" help @@ -307,6 +315,7 @@ config COREBOOT_ROMSIZE_KB default 2048 if COREBOOT_ROMSIZE_KB_2048 default 4096 if COREBOOT_ROMSIZE_KB_4096 default 8192 if COREBOOT_ROMSIZE_KB_8192 + default 12288 if COREBOOT_ROMSIZE_KB_12288 default 16384 if COREBOOT_ROMSIZE_KB_16384
# Map the config names to a hex value (bytes). @@ -320,6 +329,20 @@ config ROM_SIZE default 0x200000 if COREBOOT_ROMSIZE_KB_2048 default 0x400000 if COREBOOT_ROMSIZE_KB_4096 default 0x800000 if COREBOOT_ROMSIZE_KB_8192 + default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 + default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 + +config ALIGNED_ROM_SIZE + hex + default 0x10000 if COREBOOT_ROMSIZE_KB_64 + default 0x20000 if COREBOOT_ROMSIZE_KB_128 + default 0x40000 if COREBOOT_ROMSIZE_KB_256 + default 0x80000 if COREBOOT_ROMSIZE_KB_512 + default 0x100000 if COREBOOT_ROMSIZE_KB_1024 + default 0x200000 if COREBOOT_ROMSIZE_KB_2048 + default 0x400000 if COREBOOT_ROMSIZE_KB_4096 + default 0x800000 if COREBOOT_ROMSIZE_KB_8192 + default 0x1000000 if COREBOOT_ROMSIZE_KB_12288 default 0x1000000 if COREBOOT_ROMSIZE_KB_16384
config ENABLE_POWER_BUTTON diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c index 179822b..41be617 100644 --- a/src/mainboard/amd/dinar/agesawrapper.c +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -271,9 +271,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; + MsrReg = (0x0100000000 - CONFIG_ALIGNED_ROM_SIZE) | 5; LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 2e46516..1395591 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -45,8 +45,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* all cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + __writemsr (0x20c, (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800);
/* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index ecd85ee..ade7feb 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -166,9 +166,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + MsrReg = (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index fcbdded..2366025 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -166,9 +166,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + MsrReg = (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 58829b4..0de5a00 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -58,8 +58,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + __writemsr (0x20c, (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800);
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index af12026..c3ac439 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -46,8 +46,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + __writemsr (0x20c, (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800);
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index 6331197..8bcc9dc 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -166,9 +166,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + MsrReg = (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/torpedo/agesawrapper.c b/src/mainboard/amd/torpedo/agesawrapper.c index 8d06811..98c84bb 100644 --- a/src/mainboard/amd/torpedo/agesawrapper.c +++ b/src/mainboard/amd/torpedo/agesawrapper.c @@ -279,9 +279,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + MsrReg = (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
/* Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI */ diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index e4cd21b..af37dbb 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -45,8 +45,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + __writemsr (0x20c, (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800);
if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index b76e6a8..ef8036b 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -49,8 +49,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr(0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); - __writemsr(0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + __writemsr(0x20c, (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5); + __writemsr(0x20d, (0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800);
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr(0xc0010062, 0); diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c index 8300e34..10c4431 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ b/src/mainboard/asrock/imb-a180/agesawrapper.c @@ -166,9 +166,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + MsrReg = (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS; diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index 529878b..4e54a22 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -166,9 +166,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + MsrReg = (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS; diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 05699cc..3449005 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -60,12 +60,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - msr.lo = ((0x0100000000ull - CONFIG_ROM_SIZE) | 5) & 0xFFFFFFFF; - msr.hi = ((0x0100000000ull - CONFIG_ROM_SIZE) | 5) >> 32; + msr.lo = ((0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5) & 0xFFFFFFFF; + msr.hi = ((0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5) >> 32; wrmsr (MSR_MTRR_VARIABLE_BASE6, msr);
- msr.lo = ((0x1000000000ull - CONFIG_ROM_SIZE) | 0x800) & 0xFFFFFFFF; - msr.hi = ((0x1000000000ull - CONFIG_ROM_SIZE) | 0x800) >> 32; + msr.lo = ((0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800) & 0xFFFFFFFF; + msr.hi = ((0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800) >> 32; wrmsr (MSR_MTRR_VARIABLE_MASK6, msr);
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 093a047..248124c 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -58,8 +58,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + __writemsr (0x20c, (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800);
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 88b8100..e9eb9eb 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -58,8 +58,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + __writemsr (0x20c, (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800);
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c index 3199575..527bbc1 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c @@ -192,9 +192,9 @@ UINT32 agesawrapper_amdinitmmio(VOID) LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; + MsrReg = (0x0100000000 - CONFIG_ALIGNED_ROM_SIZE) | 5; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS; diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c index 49abe25..cf7a15e 100644 --- a/src/mainboard/supermicro/h8scm/agesawrapper.c +++ b/src/mainboard/supermicro/h8scm/agesawrapper.c @@ -192,9 +192,9 @@ UINT32 agesawrapper_amdinitmmio(VOID) LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; + MsrReg = (0x0100000000 - CONFIG_ALIGNED_ROM_SIZE) | 5; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS; diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c index 7fba1b7..b7e0791 100644 --- a/src/mainboard/tyan/s8226/agesawrapper.c +++ b/src/mainboard/tyan/s8226/agesawrapper.c @@ -202,9 +202,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + MsrReg = (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS;