Attention is currently required from: Felix Singer, Nico Huber, Frans Hendriks, Michael Niewöhner, Wim Vervoorn. Hello Felix Singer, Nico Huber, Frans Hendriks, Michael Niewöhner, Wim Vervoorn,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57262
to look at the new patch set (#2).
Change subject: skylake DDR4 boards: Set `CaVrefConfig` to 2 ......................................................................
skylake DDR4 boards: Set `CaVrefConfig` to 2
The `CaVrefConfig` FSP-M UPD describes how the on-die Vref generators are connected to the DRAM. With the exception of an early Skylake RVP board (which doesn't have coreboot support), mainboards using DDR3 or LPDDR3 memory should set `CaVrefConfig` to 0, whereas mainboards with DDR4 should set `CaVrefConfig` to 2. MRC uses this information during memory training, so it is important to use the correct value to avoid any issues, such as increased power usage, system instability or even boot failures.
However, several Skylake DDR4 mainboards don't set `CaVrefConfig` to 2. Although they can boot successfully, it's not optimal. For boards that set `DIMM_SPD_SIZE` to 512 (DDR4 SPD size), set `CaVrefConfig` to 2.
Change-Id: Idab77daff311584b3e3061e9bf107c2fc1b7bdf1 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/51nb/x210/romstage.c M src/mainboard/asrock/h110m/romstage.c M src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c M src/mainboard/facebook/monolith/romstage.c M src/mainboard/google/fizz/romstage.c M src/mainboard/kontron/bsl6/romstage.c M src/mainboard/purism/librem_skl/romstage.c M src/mainboard/supermicro/x11-lga1151-series/romstage.c 8 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/57262/2