Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36651 )
Change subject: intel/cannonlake: Implement PCIe RP devicetree update ......................................................................
Patch Set 24:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36651/24/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/duffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/36651/24/src/mainboard/google/hatch... PS24, Line 297: device pci 1c.6 on
SoC supported the RP swap.
What do you mean exactly? HW support? FSP support? coreboot support?
The history, AFAIK it, is roughly: before Sandy Bridge, we ignored the topic. From Sandy to FSP, we used the original (reset state) function numbers in the devicetree. coreboot was responsible to patch things after it switched ports. Starting with FSP, things got messy. FSP has its own mind about switching ports (can be because we asked it to disable function 0, but can also be that FSP decided to disable it because no downstream device was detected). Skylake got some code to patch the devicetree (which almost worked correctly), but other FSP platform didn't.
This new solution for FSP platforms also uses the original function numbers in the devicetree. It patches everything before PCI enumeration. So that should have no special requirements on the devicetree. The older, coreboot-native solutions had the requirement to list function 0 in the devicetree. But we used the devicetree on/off to decide if it should be disabled, so an `off` must have been valid.