Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41062 )
Change subject: soc/intel/jasperlake: Apply FiVR related settings ......................................................................
Patch Set 15:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41062/14/src/soc/intel/jasperlake/f... File src/soc/intel/jasperlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/41062/14/src/soc/intel/jasperlake/f... PS14, Line 162: /* FiVR */
Is this configuration required even if FIVR is not used/enabled. […]
Yes, Karthik. Our mainboards would use MBVR and we confirmed from our BIOS team that the following settings are common for both VCCIO MBVR and VCCIO FIVR mode.
https://review.coreboot.org/c/coreboot/+/41062/14/src/soc/intel/jasperlake/f... PS14, Line 163:
few comments […]
Added the s0ix check, Subrata. I'm guessing we wouldn't need the Kconfig now as all the boards would support MBVR and the settings are common. Please let me know your thoughts?
The hardcoded values would be updated in the PCH FIVR C Spec which would be released to the customers. Final values implemented in BIOS can be referred from here. https://hsdes.intel.com/appstore/article/#/16011001289. For now, we have also raised an HSD asking for the documentation. Please find the link here. https://hsdes.intel.com/resource/16011290106. Will we be able to proceed with this?